MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 271

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

13.2.1.2 Interrupt Mask Register (IMRHn, IMRLn)
The IMRHn and IMRLn registers are each 32 bits in size and provide a bit map for each interrupt
to allow the request to be disabled (1 = disable the request, 0 = enable the request). The IMRn is
set to all ones by reset, disabling all interrupt requests. The IMRn can be read and written. A write
that sets bit 0 of the IMR forces the other 63 bits to be set, disabling all interrupt sources, and
providing a global mask-all capability.
Freescale Semiconductor
Address
Reset
Reset
31–0
31–1
Bits
Bits
0
W
W
R
R
31
15
0
0
Name
Name
INT
30
14
INT
0
0
—
Figure 13-2. Interrupt Pending Register Low (IPRLn)
29
13
0
0
Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRHn
bit determines whether an interrupt condition can generate an interrupt. At every system
clock, the IPRHn samples the signal generated by the interrupting source. The
corresponding IPRHn bit reflects the state of the interrupt signal even if the corresponding
IMRHn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRLn
bit determines whether an interrupt condition can generate an interrupt. At every system
clock, the IPRLn samples the signal generated by the interrupting source. The
corresponding IPRLn bit reflects the state of the interrupt signal even if the corresponding
IMRLn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
Reserved, should be cleared.
IPSBAR + 0x00_0C04 (INTC0), IPSBAR + 0x00_0D04 (INTC1)
28
12
0
0
Table 13-4. IPRHn Field Descriptions
Table 13-5. IPRLn Field Descriptions
27
11
0
0
MCF5235 Reference Manual, Rev. 2
26
10
0
0
25
0
0
9
INT
24
0
0
8
INT
23
Description
Description
0
0
7
22
0
6
0
21
0
0
5
20
0
0
4
Memory Map/Register Definition
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0
0
13-7