MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 325

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

17.4 Bus Errors
Attempting to write to a range of addresses that is write protected (CSARn[WP] = 1) will not
assert the corresponding chip select. Also, an access error exception will occur. See
Section 16.4.1.2, “Chip Select Mask Registers (CSMR0–CSMR7)”
Exceptions”
17.5 Data Transfer Operation
Data transfers between the MCF5235 and other devices involve the following signals:
The address bus, write data, TS, and all attribute signals change on the rising edge of CLKOUT.
Read data is latched into the MCF5235 on the rising edge of CLKOUT.
The MCF5235 bus supports byte, word, and longword operand transfers and allows accesses to 8-,
16-, and 32-bit data ports. Aspects of the transfer, such as the port size, the number of wait states
for the external slave being accessed, and whether internal transfer termination is enabled, can be
programmed in the chip-select control registers (CSCRs) and the DRAM control registers
(DACRs).
Freescale Semiconductor
• Address bus (A[23:0])
• Data bus (D[31:0])
• Control signals (TS and TA)
• CSn, OE, BSn
• Attribute signals (R/W, TSIZ, and TIP)
Falling-Edge
Rising-Edge
CLKOUT
Signals
Signals
Inputs
t
t
t
t
vo
ho
si
hi
=Required input setup time relative to CLKOUT edge
=Required input hold time relative to CLKOUT edge
Figure 17-1. Signal Relationship to CLKOUT for Non-DRAM Access
=Propagation delay of signal relative to CLKOUT edge
=Output hold time relative to CLKOUT edge
for more details.
t
si
MCF5235 Reference Manual, Rev. 2
t
t
vo
hi
t
vo
t
and
ho
Section 3.7, “Processor
t
ho
Bus Errors
17-3