MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 355

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

request flag is set and the counter begins counting down again. The DRAM controller completes
any active burst operation and then performs a
a refresh cycle and clears the refresh request flag. This refresh cycle includes a delay from any
precharge to the auto-refresh command, the auto-refresh command, and then a delay until any
ACTV
until the cycle is completed.
Figure 18-8
refresh request becomes active. The request is delayed by the precharge to
programmed into the active SDRAM bank by the CAS bits. The
and the delay required by DCR[RTIM] is inserted before the next
this example, the next bus cycle is initiated, but does not generate an SDRAM access until T
finished. Because both chip selects are active during the
of external SDRAM.
18.3.4.5 Self-Refresh Operation
Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at the same
time to perform an internal refresh operation and to maintain the integrity of the data stored in the
SDRAM. The DRAM controller supports self-refresh with DCR[IS]. When IS is set, the
command is sent to the SDRAM. When IS is cleared, the
controller.
Freescale Semiconductor
SD_CS[0] or [1]
SD_SRAS
SD_SCAS
CLKOUT
SD_WE
command is allowed. Any SDRAM access initiated during the auto-refresh cycle is delayed
A[31:0]
Figure 18-9
shows the auto-refresh timing. In this case, there is an SDRAM access when the
PALL
t
RCD
shows the self-refresh operation.
= 2
Figure 18-8. Auto-Refresh Operation
MCF5235 Reference Manual, Rev. 2
REF
PALL
operation. The DRAM controller then initiates
t
REF
RC
= 6
SELFX
command, it is passed to both blocks
REF
ACTV
command is sent to the DRAM
command is then generated
command is generated. In
Memory Map/Register Definition
ACTV
ACTV
delay
RC
SELF
18-17
is