MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 54

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Overview
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1.3.10 I
C Bus
The I
C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data
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exchange, minimizing the interconnection between devices. This bus is suitable for applications
requiring occasional communications over a short distance between many devices.
1.3.11 QSPI
The queued serial peripheral interface module provides a high-speed synchronous serial peripheral
interface with queued transfer capability. It allows up to 16 transfers to be queued at once,
eliminating CPU intervention between transfers.
1.3.12 Cryptography
The superset device, MCF5235, incorporates small, fast, dedicated hardware accelerators for
random number generation, message digest and hashing, and the DES, 3DES, and AES block
cipher functions allowing for the implementation of common Internet security protocol
cryptography operations with performance well in excess of software-only algorithms.
1.3.13 DMA Timers (DTIM0-DTIM3)
There are four independent, DMA-transfer-generating 32-bit timers (DTIM[3:0]) on the
MCF5235. Each timer module incorporates a 32-bit timer with a separate register set for
configuration and control. The timers can be configured to operate from the system clock or from
an external clock source using one of the DTINn signals. If the system clock is selected, it can be
divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler
which clocks the actual timer counter register (TCRn). Each of these timers can be configured for
input capture or reference compare mode. By configuring the internal registers, each timer may be
configured to assert an external signal, generate an interrupt on a particular event or cause a DMA
transfer.
1.3.14 Periodic Interrupt Timers (PIT0-PIT3)
The four periodic interrupt timers (PIT[3:0]) are 16-bit timers that provide precise interrupts at
regular intervals with minimal processor intervention. Each timer can either count down from the
value written in its PIT modulus register, or it can be a free-running down-counter.
1.3.15 Software Watchdog Timer
The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog
counter is a free-running down-counter that generates a reset on underflow. To prevent a reset,
software must periodically restart the countdown.
MCF5235 Reference Manual, Rev. 2
1-14
Freescale Semiconductor