MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 267
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
- Current page: 267 of 754
- Download datasheet (13Mb)
The level and priority is fully programmable for all sources except interrupt sources 1–7. Interrupt
source 1–7 (IRQ[1:7] from the Edgeport module) are fixed at the corresponding level’s midpoint
priority. Thus, a maximum of 8 fully-programmable interrupt sources are mapped into a single
interrupt level. The “fixed” interrupt source is hardwired to the given level, and represents the
mid-point of the priority within the level. For the fully-programmable interrupt sources, the 3-bit
level and the 3-bit priority within the level are defined in the 8-bit interrupt control register
(ICRnx).
The operation of the interrupt controller can be broadly partitioned into three activities:
13.1.2.1 Interrupt Recognition
The interrupt controller continuously examines the request sources and the interrupt mask register
to determine if there are active requests. This is the recognition phase.
13.1.2.2 Interrupt Prioritization
As an active request is detected, it is translated into the programmed interrupt level, and the
resulting 7-bit decoded priority level (IRQ[7:1]) is driven out of the interrupt controller. The
decoded priority levels from all the interrupt controllers are logically summed together and the
highest enabled interrupt request is then encoded into a 3-bit priority level that is sent to the
processor core during this prioritization phase.
Freescale Semiconductor
• Recognition
• Prioritization
• Vector determination during IACK
Table 13-1. Interrupt Priority Within a Level
ICR[2:0]
110
101
100
011
010
001
000
111
—
MCF5235 Reference Manual, Rev. 2
Fixed Midpoint Priority
7 (Highest)
0 (Lowest)
Priority
6
5
4
3
2
1
Interrupt
Sources
8–63
8–63
8–63
8–63
8–63
8–63
8–63
8–63
1–7
Introduction
13-3
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