MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 303

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

If DSIZE is another size, data writes are optimized to write the largest size allowed based on the
address, but not exceeding the configured size.
14.4.4.3 Bandwidth Control
Bandwidth control makes it possible to force the DMA off the bus to allow access to another
device. DCRn[BWC] provides seven levels of block transfer sizes. If the BCRn decrements to a
multiple of the decode of the BWC, the DMA bus request negates until the bus cycle terminates.
If a request is pending, the arbiter may then pass bus mastership to another device. If
auto-alignment is enabled, DCRn[AA] = 1, the BCRn may skip over the programmed boundary,
in which case, the DMA bus request is not negated.
If BWC = 000, the request signal remains asserted until BCRn reaches zero. DMA has priority
over the core. Note that in this scheme, the arbiter can always force the DMA to relinquish the bus.
See
14.4.5 Termination
An unsuccessful transfer can terminate for one of the following reasons:
Freescale Semiconductor
• Error conditions—When the MCF5235 encounters a read or write cycle that terminates
• Interrupts—If DCRn[INT] is set, the DMA drives the appropriate internal interrupt signal.
Section 11.3.3, “Bus Master Park Register
with an error condition, DSRn[BES] is set for a read and DSRn[BED] is set for a write
before the transfer is halted. If the error occurred in a write cycle, data in the internal
holding register is lost.
The processor can read DSRn to determine whether the transfer terminated successfully or
with an error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE
and error bits.
MCF5235 Reference Manual, Rev. 2
(MPARK).”
Functional Description
14-19