MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 525

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Figure 25-4
25.3.2 QSPI Delay Register (QDLYR)
Figure 25-5
Freescale Semiconductor
QSPI_DOUT
QSPI_CLK
QSPI_DIN
QSPI_CS
Address
Reset
14–8
Bits
7–0
15
W
R SPE
shows an example of a QSPI clocking and data transfer.
shows the QDLYR.
15
0
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
msb
15
15
Name
QCD
SPE
DTL
14
0
Figure 25-4. QSPI Clocking and Data Transfer Example
A
14
14
13
0
13
13
QSPI enable. When set, the QSPI initiates transfers in master mode by executing
commands in the command RAM. Automatically cleared by the QSPI when a transfer
completes. The user can also clear this bit to abort transfer unless QIR[ABRTL] is set. The
recommended method for aborting transfers is to set QWR[HALT].
QSPICLK delay. When the DSCK bit in the command RAM is set this field determines the
length of the delay from assertion of the chip selects to valid QSPI_CLK transition.
Delay after transfer. When the DT bit in the command RAM is set this field determines the
length of delay after the serial transfer.
Figure 25-5. QSPI Delay Register (QDLYR)
12
Table 25-5. QDLYR Field Descriptions
0
12
12
QCD
11
11
11
0
MCF5235 Reference Manual, Rev. 2
10
10
10
1
9
9
IPSBAR + 0x00_0344
0
9
8
8
0
8
7
7
6
6
Description
0
7
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
5
5
6
0
4
4
0
5
3
3
0
4
2
2
DTL
Memory Map/Register Definition
1
1
0
3
0
0
1
2
B
0
1
0
0
25-11