MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 52

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Overview
captured operand data, and branch target addresses defining processor activity at the CPU’s clock
rate.
The integration of the eTPU on the MCF5235 family marks the first time that ColdFire and eTPU
debug subsystems have been present in a single device. The eTPU’s debug functionality has been
merged into the standard ColdFire debug model. This includes access to the eTPU debug registers
via the standard ColdFire BDM serial interface or the processor WDEBUG instruction and
run/halt cross triggering capability between eTPU debug and ColdFire BDM.
1.3.5
The MCF5235 supports circuit board test strategies based on the Test Technology Committee of
IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP)
consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass
register, a 330-bit boundary-scan register, and a 32-bit ID register). The boundary scan register
links the device’s pins into one shift register. Test logic, implemented using static logic design, is
independent of the device system logic.
The MCF5235 implementation can do the following:
1.3.6
1.3.6.1
The 8-Kbyte cache can be configured into one of three possible organizations: an 8-Kbyte
instruction cache, an 8-Kbyte data cache or a split 4-Kbyte instruction/4-Kbyte data cache. The
configuration is software-programmable by control bits within the privileged Cache Configuration
Register (CACR). In all configurations, the cache is a direct-mapped single-cycle memory,
organized as 512 lines, each containing 16 bytes of data. The memories consist of a 512-entry tag
array (containing addresses and control bits) and a 8-Kbyte data array, organized as 2048 x 32 bits.
If the desired address is mapped into the cache memory, the output of the data array is driven onto
the ColdFire core's local data bus, completing the access in a single cycle. If the data is not mapped
into the tag memory, a cache miss occurs and the processor core initiates a 16-byte line-sized fetch.
The cache module includes a 16-byte line fill buffer used as temporary storage during miss
1-12
• Perform boundary-scan operations to test circuit board electrical continuity
• Sample MCF5235 system pins during operation and transparently shift out the result in the
• Bypass the MCF5235 for a given circuit board test by effectively reducing the
• Disable the output drive to pins during circuit-board testing
• Drive output pins to stable levels
boundary scan register
boundary-scan register to a single bit
JTAG
On-chip Memories
Cache
MCF5235 Reference Manual, Rev. 2
Freescale Semiconductor