MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 578

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

I
27.5.3 I
The I2CR is used to enable the I
operation as a slave or a master.
27-10
2
C Interface
Bits
7
6
5
4
3
2
C Control Register (I2CR)
Name
MSTA
TXAK
MTX
IIEN
Address
IEN
Reset
W
R
I
in the middle of a byte transfer, slave mode ignores the current bus transfer and starts
operating when the next START condition is detected. Master mode is not aware that the
bus is busy; so initiating a start cycle may corrupt the current bus cycle, ultimately causing
either the current master or the I
returns to normal.
0 The I
1 The I
I
0 I
1 I
Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without
generating a STOP signal.
0 Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode.
1 Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects
Transmit/receive mode select bit. Selects the direction of master and slave transfers.
0 Receive
1 Transmit. When the device is addressed as a slave, software should set MTX according
Transmit acknowledge enable. Specifies the value driven onto I2C_SDA during
acknowledge cycles for both master and slave receivers. Note that writing TXAK applies
only when the I
0 An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte
1 No acknowledge signal response is sent (that is, acknowledge bit = 1).
2
2
C enable. Controls the software reset of the entire I
C interrupt enable.
IEN
Figure 27-11. I
effect.
cleared.
master mode.
to I2SR[SRW]. In master mode, MTX should be set according to the type of transfer
required. Therefore, when the MCU addresses a slave device, MTX is always 1.
of data.
0
7
2
2
C module interrupts are disabled, but currently pending interrupt condition are not
C module interrupts are enabled. An I
Table 27-4. I2CR Field Descriptions
2
2
C module is disabled, but registers can still be accessed.
C module is enabled. This bit must be set before any other I2CR bits have any
2
IIEN
C module and the I
MCF5235 Reference Manual, Rev. 2
0
6
2
C bus is a receiver.
MSTA
0
5
2
C Control Register (I2CR)
IPSBAR + 0x00_0308
MTX
0
4
2
C module to lose arbitration, after which bus operation
2
TXAK
C interrupt. It also contains bits that govern
Description
0
3
2
C interrupt occurs if I2SR[IIF] is also set.
RSTA
2
0
2
C module. If the module is enabled
0
1
0
0
0
0
Freescale Semiconductor