MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 469

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Freescale Semiconductor
Reg Addr
• If the FlexCAN state is error-passive, and either TXECTR or RXECTR decrements to a
• If the value of TXECTR increases to be greater than 255, the ERRSTATn[FLTCONF] field
• If FlexCAN is in bus off state, then TXECTR is cascaded together with another internal
• If during system start-up, only one node is operating, then its TXECTR increases in each
• If the RXECTR increases to a value greater than 127, it is not incremented further, even if
Reset
Reset
31–16
value less than or equal to 127 while the other already satisfies this condition, the
ERRSTATn[FLTCONF] field is updated to reflect error-active state.
is updated to reflect bus off state, and an interrupt may be issued. The value of TXECTR is
then reset to zero.
counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
TXECTR is reset to zero and counts in a manner where the internal counter counts 11 such
bits and then wraps around while incrementing the TXECTR. When TXECTR reaches the
value of 128, the ERRSTATn[FLTCONF] field is updated to be error-active and both error
counters are reset to zero. At any instance of dominant bit following a stream of less than
11 consecutive recessive bits, the internal counter resets itself to zero without affecting the
TXECTR value.
message it is trying to transmit, as a result of acknowledge errors (indicated by the
ERRSTATn[ACKERR] bit). After the transition to error-passive state, the TXECTR does
not increment anymore by acknowledge errors. Therefore the device never goes to the bus
off state.
more errors are detected while being a receiver. At the next successful message reception,
the counter is set to a value between 119 and 127 to resume to error-active state.
Bits
W
W
R
R
31
15
0
0
0
Name
Figure 21-8. FlexCAN Error Counter Register (ERRCNTn)
30
14
—
0
0
0
29
13
0
0
0
Reserved, should be cleared.
Table 21-6. ERRCNTn Field Descriptions
RXECTR
28
12
0
0
0
IPSBAR + 0x1C_001C (CAN0); 0x1F_001C (CAN1)
27
11
MCF5235 Reference Manual, Rev. 2
0
0
0
26
10
0
0
0
25
0
0
0
9
24
0
0
0
8
Description
23
0
0
7
0
22
0
0
0
6
21
0
0
0
5
20
TXECTR
0
0
0
4
Memory Map/Register Definition
19
0
0
3
0
18
0
0
0
2
17
0
0
0
1
16
0
0
0
0
21-15