MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 441

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

20.6.2.3 Global Channel Registers
The registers in this section group, by type, the interrupt status and enable bits from all the
channels. This organization eases management of all channels or groups of channels by a single
interrupt handler routine. These bits are mirrored by the individual channel registers.
20.6.2.3.1 eTPU Channel Interrupt Status Register (ETPU_CISR)
Host interrupt status from all channels are grouped in ETPU_CISR. The bits are mirrored by the
channels’ status/control registers. For more information, refer to
Channel n Status Control Register
Freescale Semiconductor
Address
31–24
23–0
31–0
Bits
Bits
Reset
Reset
W
W
R
R
Figure 20-10. eTPU Channel Interrupt Status Register (ETPU_CISR)
The host CPU must write 1 to clear a status bit.
31
15
0
0
Name
Name
Read:
TCR2
Write:
CICn
CISn
—
30
14
0
0
Table 20-9. ETPU_TB2R Bit Field Descriptions
29
13
0
0
Table 20-10. ETPU_CISR Field Descriptions
Reserved.
TCR2 value. Used on matches and captures. For information on TCR2, refer to the eTPU
User’s Manual.
Channel n interrupt status.
0 Indicates that channel n has no pending interrupt to the host CPU.
1 Indicates that channel n has a pending interrupt to the host CPU.
Channel n interrupt clear
0 Keep interrupt status bit unaltered.
1 Clear interrupt status bit.
For details about interrupts refer to the eTPU User’s Manual.
28
12
0
0
MCF5235 Reference Manual, Rev. 2
27
11
0
0
(ETPU_CnSCR),” and the eTPU User’s Manual.
26
10
0
0
IPSBAR + 0x1D_0200
25
0
0
9
NOTE
24
0
0
8
CIC]
CIS
CIS
CIC
Description
Description
23
0
0
7
22
0
0
6
21
0
0
5
20
0
4
0
Section 20.6.2.4.3, “eTPU
Memory Map/Register Definition
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0
20-27