MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 412

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Fast Ethernet Controller (FEC)
19.3.14.1.4 Heartbeat
Some transceivers have a self-test feature called “heartbeat” or “signal quality error.” To signify a
good self-test, the transceiver indicates a collision to the FEC within 4 microseconds after
completion of a frame transmitted by the Ethernet controller. This indication of a collision does
not imply a real collision error on the network, but is rather an indication that the transceiver still
seems to be functioning properly. This is called the heartbeat condition.
If the HBC bit is set in the TCR register and the heartbeat condition is not detected by the FEC
after a frame transmission, then a heartbeat error occurs. When this error occurs, the FEC closes
the buffer, sets the HB bit in the EIR register, and generates the HBERR interrupt if it is enabled.
19.3.14.2 Reception Errors
19.3.14.2.1Overrun Error
If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets
the OV bit in the RxBD. All subsequent data in the frame will be discarded and subsequent frames
may also be discarded until the receive FIFO is serviced by the DMA and space is made available.
At this point the receive frame/status word is written into the FIFO with the OV bit set. This frame
must be discarded by the driver.
19.3.14.2.2Non-Octet Error (Dribbling Bits)
The Ethernet controller handles up to seven dribbling bits when the receive frame terminates past
an non-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a
CRC error, then the frame non-octet aligned (NO) error is reported in the RxBD. If there is no CRC
error, then no error is reported.
19.3.14.2.3CRC Error
When a CRC error occurs with no dribble bits, the FEC closes the buffer and sets the CR bit in the
RxBD. CRC checking cannot be disabled, but the CRC error can be ignored if checking is not
required.
19.3.14.2.4Frame Length Violation
When the receive frame length exceeds MAX_FL bytes the BABR interrupt will be generated, and
the LG bit in the end of frame RxBD will be set. The frame is not truncated unless the frame length
exceeds 2032 bytes).
MCF5235 Reference Manual, Rev. 2
19-48
Freescale Semiconductor