MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 300

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

DMA Controller Module
Figure 14-9
shows the minimum 4-clock cycle delay from when DREQn is sampled asserted to
when a DMA bus cycle begins. This delay may be longer, depending on DMA priority, bus
arbitration, and other factors.
Figure 14-9
shows the relationship between the assertion of a
properly enabled DREQn, the DMA acknowledge, and the activation of the channel for a transfer
where both the source and destination are mapped to chip select memories on the external bus.
0
1
2
3
4
5
6
7
8
9
10
CLKIN
DREQn
DACKn
TS
CS
TA
R/W
A[23:0]
Read
Write
n
Figure 14-9. DREQ
Timing Constraints, Dual-Address DMA Transfer
Once the DMA module has detected the assertion of a properly-enabled DREQn, it responds with
a 1-cycle assertion of an acknowledge signal. This request/acknowledge handshake is provided so
the request can be negated.
Since bus timings can vary from device to device, the diagrams below are conditionalized for 5210
only. The information is really just a repeat from the EIM/FlexBus and SDRAMC chapters, so the
customers should not need this information. -MH
Figure 14-10
shows a dual-address, external peripheral-to-SDRAM DMA transfer. The DMA is
not parked on the bus, so the diagram shows how the CPU can generate multiple bus cycles during
DMA transfers. In cycle-steal mode, the maximum length of DREQ assertion to maintain a single
transfer is configuration-dependent. To avoid multiple transfers, for single-address accesses, no
hold signal, byte accesses, and idle channels, DREQ may be asserted for no more than four clock
cycles.
MCF5235 Reference Manual, Rev. 2
14-16
Freescale Semiconductor