MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 289

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

14.3.1 DMA Request Control (DMAREQC)
The DMAREQC register provides a software-controlled connection matrix for DMA requests. It
logically routes DMA requests from the DMA timers and UARTs to the four channels of the DMA
controller. Writing to this register determines the exact routing of the DMA request to the four
channels of the DMA modules. If DCRn[EEXT] is set and the channel is idle, the assertion of the
appropriate DREQn activates channel n (eTPU request assertion will activate DMA channel 3).
Freescale Semiconductor
Address
Reset
Reset
31–20
19-16
Bits
W
W
R
R
31
15
0
0
0
DMAREQC
Name
_EXT
30
14
0
0
0
Figure 14-3. DMA Request Control Register (DMAREQC)
DMAC3
—
29
13
0
0
0
Reserved, should be cleared.
DMA request control for external (off-chip) and eTPU requests. The DMAREQC_EXT[3:0]
bits correspond to DMA channels 3, 2, 1, and 0. If set, the corresponding DMACn bit field
is ignored. If cleared, refer to the appropriate DMACn bit field for configuring the internal
DMA requestor.
DMAREQC_EXT[3] controls the eTPU request, while DMAREQC_EXT[2:0] controls the
external DMA request/acknowledge signals. In order for an external or eTPU request to
activate a DMA channel the corresponding DCRn[EEXT] bit must be set as well.
Note: GPIO must be configured to enable external DMA requests.
Table 14-2. DMAREQC Field Description
28
12
0
0
0
0
1
27
11
0
0
0
MCF5235 Reference Manual, Rev. 2
DMAREQC_
See DMAC3
26
10
0
0
0
DMAC2
EXT[3]
eTPU
25
IPSBAR + 0x00_0014
0
0
0
9
24
0
0
0
8
DMAREQC_
See DMAC2
External
DREQ2
EXT[2]
23
Description
0
0
0
7
22
0
0
6
DMAC1
0
External DREQ1
21
0
0
0
5
DMAREQC_
See DMAC1
EXT[1]
20
0
0
0
4
Memory Map/Register Definition
19
0
0
3
DMAREQC_EXT
DMAREQC_
See DMAC0
18
0
DMAC0
0
2
External
DREQ0
EXT[0]
17
0
0
1
16
0
0
0
14-5