MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 648

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Debug Support
two 4-bit nibbles: one nibble allows the processor to transmit processor status, (PST), and the other
allows operand data to be displayed (debug data, DDATA). The processor status may not be related
to the current bus transfer.
External development systems can use PST outputs with an external image of the program to
completely track the dynamic execution path. This tracking is complicated by any change in flow,
especially when branch target address calculation is based on the contents of a program-visible
register (variant addressing). DDATA outputs can be configured to display the target address of
such instructions in sequential nibble increments across multiple processor clock cycles, as
described in
elements form a FIFO buffer connecting the processor’s high-speed local bus to the external
development system through PST[3:0] and DDATA[3:0]. The buffer captures branch target
addresses and certain data values for eventual display on the DDATA port, one nibble at a time
starting with the least significant bit (lsb).
Execution speed is affected only when both storage elements contain valid data to be dumped to
the DDATA port. The core stalls until one FIFO entry is available.
Table 32-2
32-4
PST[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
shows the encoding of these signals.
Section 32.3.1, “Begin Execution of Taken Branch (PST = 0x5).”
Continue execution. Many instructions execute in one processor cycle. If an instruction requires more
processor clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.
Begin execution of one instruction. For most instructions, this encoding signals the first processor clock
cycle of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA
instructions, generate different encodings.
Reserved
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to
enter user mode.
Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug
and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly
to the DDATA port, independent of debug module configuration. When WDDATA is executed, a value of
0x4 is signaled on the PST port, followed by the appropriate marker, and then the data transfer on the
DDATA port. Transfer length depends on the WDDATA operand size.
Begin execution of taken branch. For some opcodes, a branch target address may be displayed on
DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed,
indicated by the PST marker value preceding the DDATA nibble that begins the data output. See
Section 32.3.1, “Begin Execution of Taken Branch (PST = 0x5).”
Reserved
Begin execution of return from exception (RTE) instruction.
Table 32-2. Processor Status Encoding
MCF5235 Reference Manual, Rev. 2
Definition
Freescale Semiconductor
Two 32-bit storage