MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 261

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

12.3.1.8.5 QSPI Drive Strength Control Register (DSCR_QSPI)
The DSCR_QSPI register controls the output drive strengths of the following pins: QSPI_CS1,
QSPI_CS0, QSPI_SCK, QSPI_DIN, and QSPI_DOUT.
Freescale Semiconductor
Bits
7–1
Bits
0
7
6
5
4
3
2
1
0
Figure 12-48. QSPI Drive Strength Control Register (DSCR_QSPI)
DSCR_QSPI QSPI drive strength. This bit sets the drive strength on the QSPI_CS1, QSPI_CS0,
DSCR_IRQ IRQ drive strength. This bit sets the drive strength on the IRQ[7:1] pins.
DSCR_
DSCR_
DSCR_
UART2
UART1
UART0
Name
Address
Name
—
—
—
—
—
Reset
W
R
Note: Reset state is 0 when RCON = 1 and is the value of D[21] when
RCON = 0
Table 12-22. DSCR_UART Field Descriptions
Table 12-23. DSCR_QSPI Field Descriptions
Reserved, should be cleared.
0 IRQ[7:1] pins set at low drive
1 IRQ[7:1] pins set at high drive
Reserved, should be cleared.
UART2 drive strength. This bit sets the drive strength on the U2RXD and U2TXD pins.
0 U2RXD, U2TXD pins set at low drive
1 U2RXD, U2TXD pins set at high drive
Reserved, should be cleared.
UART1 drive strength. This bit sets the drive strength on the U1RXD, U1TXD, U1CTS, and
U1RTS pins.
0 U1RXD, U1TXD, U1CTS, and U1RTS pins set at low drive
1 U1RXD, U1TXD, U1CTS, and U1RTS pins set at high drive
Reserved, should be cleared.
UART0 drive strength. This bit sets the drive strength on the U0RXD, U0TXD, U0CTS, and
U0RTS pins.
0 U0RXD, U0TXD, U0CTS, and U0RTS pins set at low drive
1 U0RXD, U0TXD, U0CTS, and U0RTS pins set at high drive
Reserved, should be cleared.
QSPI_SCK, QSPI_DIN, and QSPI_DOUT pins.
0 Pins set at low drive
1 Pins set at high drive
0
0
7
0
0
6
MCF5235 Reference Manual, Rev. 2
0
0
5
IPSBAR + 0x10_0054
0
0
4
Description
0
0
3
Description
2
0
0
1
0
0
See Note
Memory Map/Register Definition
DSCR_
QSPI
0
12-33