MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 403

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Functional Description
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes
may occur, but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.
After the first 6 bytes of the frame have been received, the FEC performs address recognition on
the frame.
Once a collision window (64 bytes) of data has been received and if address recognition has not
rejected the frame, the receive FIFO is signalled that the frame is “accepted” and may be passed
on to the DMA. If the frame is a runt (due to collision) or is rejected by address recognition, the
receive FIFO is notified to “reject” the frame. Thus, no collision fragments are presented to the
user except late collisions, which indicate serious LAN problems.
During reception, the Ethernet controller checks for various error conditions and once the entire
frame is written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word
contains the M, BC, MC, LG, NO, CR, OV and TR status bits, and the frame length. See
Section 19.3.14.2, “ Reception
Errors” for more details.
Receive Buffer (RXB) and Frame Interrupts (RFINT) may be generated if enabled by the EIMR
register. A receive error interrupt is babbling receiver error (BABR). Receive frames are not
truncated if they exceed the max frame length (MAX_FL); however, the BABR interrupt will
occur and the LG bit in the Receive Buffer Descriptor (RxBD) will be set. See
Section 19.2.5.2,
“Ethernet Receive Buffer Descriptors (RxBD0 &
RxBD1)” for more details.
When the receive frame is complete, the FEC sets the L-bit in the RxBD, writes the other frame
status bits into the RxBD, and clears the E-bit. The Ethernet controller next generates a maskable
interrupt (RFINT bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame has been
received and is in memory. The Ethernet controller then waits for a new frame.
The Ethernet controller receives serial data lsb first.
19.3.8 Ethernet Address Recognition
The FEC filters the received frames based on destination address (DA) type — individual
(unicast), group (multicast), or broadcast (all-ones group address). The difference between an
individual address and a group address is determined by the I/G bit in the destination address field.
A flowchart for address recognition on received frames is illustrated in the figures below.
Address recognition is accomplished through the use of the receive block and microcode running
on the microcontroller. The flowchart shown in
Figure 19-27
illustrates the address recognition
decisions made by the receive block, while
Figure 19-28
illustrates the decisions made by the
microcontroller.
If the DA is a broadcast address and broadcast reject (RCR[BC_REJ]) is deasserted, then the frame
will be accepted unconditionally, as shown in
Figure
19-27. Otherwise, if the DA is not a broadcast
address, then the microcontroller runs the address recognition subroutine, as shown in
Figure
19-28.
MCF5235 Reference Manual, Rev. 2
Freescale Semiconductor
19-39