MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 697

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Freescale Semiconductor
23–15
Bits
31
30
29
28
27
26
25
24
14
Name
CLKS
CHW
PINS
CBT
EBC
CBR
CBI
—
—
—
Stop pins in debug mode. Controls whether the eTPU pins are sampled when the eTPU
eTPU CHAN register write trace. Enables tracing of wires to the CHAN register in the eTPU
execution unit. Requires channel being serviced to have program trace enabled.
0 Tracing enabled for CHAN writes
1 Tracing disabled
enters debug mode. When set, the pins are not sampled during debug mode or when
executing a forced instruction from the microinstruction register. The pins are sampled
during normal single steps.
0 Sample pins in the halted state
1 Stop sampling pins in the halted state
Stop TCR clocks. When in debug mode, controls the TCR clocks from the eTPU.
0 Do not stop TCR clocks
1 Stop TCR clocks
Client breakpoint timing. Controls the timing of the eTPU halt due to an external breakpoint
source. CBI must be set for be to have any affect.
0 If CBI=1, halt at the end of current microcycle
1 If CBI=1, halt at the completion of the current instruction thread
Reserved, should be cleared.
EVTO breakpoint controller. Controls gneration of EVTO due to a system reset, DBR
assertion or any of the following breakpoint types: Software, EVTO, MISC error, illegal
instruction, single step or external breakpoint.
0 Breakpoint status output on EVTO
1 Breakpoint status not output on EVTO
Reserved, should be cleared.
Clear breakpoint request. Clears breakpoint requests caused by internal (data write, CHAN
register write, channel service, address match, illegal instruction), software, EVTI, MISC
error, and single step breakpoints. Bit is self clearing one cycle later. Always read as zero.
The eTPU should always execute the first instruction after exiting a breakpoint condition, in
such a way that it does not halt twice at the same position. External breakpoints are not
cleared by the assertion of this bit.
0 No action
1 Clear breakpoint requests.
Reserved, should be cleared.
Client breakpoint input. Along with CBT, controls the action taken on external breakpoints.
The external breakpoint is cleared only if CBI is zero or if the external breakpoint is negated.
0 Do not halt for ColdFire core breakpoints
1 Halt for ColdFire core breakpoints
Table 32-28. DC Field Descriptions
MCF5235 Reference Manual, Rev. 2
Description
eTPU Debug Programming Model
32-53