MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 643

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

when a device other than the ColdFire processor is the device under test on a board design with
multiple chips on the overall boundary scan chain. The shift register lsb is forced to logic 0 on the
rising edge of TCLK after entry into the capture-DR state. Therefore, the first bit shifted out after
selecting the bypass register is always logic 0. This differentiates parts that support an IDCODE
register from parts that support only the bypass register.
31.4.3.9 ACCESS_AUX_TAP_eTPU Instruction
The ACCESS_AUX_TAP_eTPU instruction allows the eTPU Nexus TAP controller to gain
access to the JTAG pins. When this instruction is loaded, any data input via TDI and TMS is passed
to the Nexus TAP controller, and any TDO output from the eTPU is sent to the JTAG controller to
be output on the JTAG pins. The JTAG controller regains the port during the UPDATE-DR state
if the PAUSE-DR state was entered. The Nexus TAP controller is held in the RUN-TEST/IDLE
while it is inactive.
31.5 Initialization/Application Information
31.5.1 Restrictions
The test logic is a static logic design, and TCLK can be stopped in either a high or low state without
loss of data. However, the system clock is not synchronized to TCLK internally. Any mixed
operation using both the test logic and the system functional logic requires external
synchronization.
Using the EXTEST instruction requires a circuit-board test environment that avoids
device-destructive configurations in which MCU output drivers are enabled into actively driven
networks.
Low-power stop mode considerations:
31.5.2 Nonscan Chain Operation
Keeping the TAP controller in the test-logic-reset state ensures that the scan chain test logic is
transparent to the system logic. It is recommended that TMS, TDI, TCLK, and TRST be pulled
Freescale Semiconductor
• The TAP controller must be in the test-logic-reset state to either enter or remain in the
• The TCLK input is not blocked in low-power stop mode. To consume minimal power, the
• The TMS, TDI, and TRST pins include on-chip pull-up resistors. For minimal power
low-power stop mode. Leaving the test-logic-reset state negates the ability to achieve
low-power, but does not otherwise affect device functionality.
TCLK input should be externally connected to V
consumption in low-power stop mode, these three pins should be either connected to V
or left unconnected.
MCF5235 Reference Manual, Rev. 2
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Initialization/Application Information
31-11
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