MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 464

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

FlexCAN
21-10
31–24
23–22
21–19
18–16
11–8
Bits
15
14
13
12
BOFFMSK Bus off interrupt mask.
CLK_SRC Clock source. Selects the clock source for the CAN interface to be fed to the prescalar. This
PRESDIV
ERRMSK
PSEG1
PSEG2
Name
RJW
LPB
—
Prescaler division factor. Defines the ratio between the clock source frequency (set by
CLK_SRC bit) and the serial clock (S clock) frequency. The S clock period defines the time
quantum of the CAN protocol. For the reset value, the S clock frequency is equal to the
clock source frequency. The maximum value of this register is 0xFF, that gives a minimum
S clock frequency equal to the clock source frequency divided by 256. For more
information refer to
Resyncronization jump width. Defines the maximum number of time quanta (one time
quantum is equal to the S clock period) that a bit time can be changed by one
resynchronization. The valid programmable values are 0–3.
Phase buffer segment 1. Defines the length of phase buffer segment 1 in the bit time. The
valid programmable values are 0–7.
Phase buffer segment 2. Defines the length of phase buffer segment 2 in the bit time. The
valid programmable values are 1–7.
0 Bus off interrupt disabled
1 Bus off interrupt enabled
Error interrupt mask.
0 Error interrupt disabled
1 Error interrupt enabled
bit should only be changed while the module is disabled.
0 Clock source is EXTAL
1 Clock source is the internal bus clock, f
Loop back. Configures FlexCAN to operate in loop-back mode. In this mode, FlexCAN
performs an internal loop back that can be used for self test operation. The bit stream
output of the transmitter is fed back internally to the receiver input. The Rx CAN input pin
is ignored and the Tx CAN output goes to the recessive state (logic 1). FlexCAN behaves
as it normally does when transmitting, and treats its own transmitted message as a
message received from a remote node. In this mode, FlexCAN ignores the bit sent during
the ACK slot in the CAN frame acknowledge field, generating an internal acknowledge bit
to ensure proper reception of its own message. Both transmit and receive interrupts are
generated.
0 Loop back disabled
1 Loop back enabled
Reserved, should be cleared.
Table 21-3. CANCTRLn Field Descriptions
MCF5235 Reference Manual, Rev. 2
Phase buffer segment 2
Phase buffer segment 1
Section 21.4.8, “Bit
Resync jump width = (RJW + 1) time quanta
S clock frequency
Description
Timing.”
sys/2
=
=
=
(PSEG2 + 1) time quanta
(PSEG1 + 1) time quanta
f sys/2 or EXTAL
----------------------------------------- -
PRESDIV + 1
Freescale Semiconductor