MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 388

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Fast Ethernet Controller (FEC)
19.2.4.17 Descriptor Group Lower Address Register (GALR)
The GALR register is written by the user. This register contains the lower 32 bits of the 64-bit hash
table used in the address recognition process for receive frames with a multicast address. This
register must be initialized by the user.
19.2.4.18 FIFO Transmit FIFO Watermark Register (TFWR)
The TFWR is a 2-bit read/write register programmed by the user to control the amount of data
required in the transmit FIFO before transmission of a frame can begin. This allows the user to
minimize transmit latency (TFWR = 0x) or allow for larger bus access latency (TFWR = 11) due
to contention for the system bus. Setting the watermark to a high value will minimize the risk of
transmit FIFO underrun due to contention for the system bus. The byte counts associated with the
TFWR field may need to be modified to match a given system requirement (worst case bus access
latency by the transmit data DMA channel).
19-24
Address
Reset
Reset
31–0
31–0
Bits
Bits
W
W
R
R
—
—
31
15
Figure 19-18. Descriptor Group Lower Address Register (GALR)
GADDR1
GADDR2
Name
Name
—
—
30
14
—
—
29
13
The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the
address recognition process for receive frames with a multicast address. Bit 31 of
GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the
address recognition process for receive frames with a multicast address. Bit 31 of
GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
—
—
Table 19-20. GAUR Field Descriptions
28
12
Table 19-21. GALR Field Descriptions
—
—
27
11
MCF5235 Reference Manual, Rev. 2
—
—
26
10
25
—
—
9
IPSBAR + 0x1124
GADDR2
GADDR2
—
—
24
8
23
—
—
Description
Description
7
—
—
22
6
—
—
21
5
—
—
20
4
—
—
19
3
Freescale Semiconductor
—
—
18
2
—
—
17
1
16
—
—
0