MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 291

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

14.3.3 Destination Address Registers (DAR0–DAR3)
DARn, shown in
14.3.4 Byte Count Registers (BCR0–BCR3) and DMA Status
BCRn, shown in
BCRn decrements on the successful completion of the address transfer of a write transfer. BCRn
decrements by 1, 2, 4, or 16 for byte, word, longword, or line accesses, respectively.
Freescale Semiconductor
Address
Address
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
Figure 14-6. Byte Count Registers (BCRn) and Status Registers (DSRn)
Registers (DSR0–DSR3)
31
15
31
15
0
0
0
0
The DMA does not maintain coherency with the cache. Therefore,
DMAs should not transfer data to cacheable memory unless software
is used to maintain the cache coherency.
Figure
Figure
30
14
30
14
0
0
0
0
Figure 14-5. Destination Address Registers (DARn)
29
13
29
13
0
0
0
0
14-6, contains the number of bytes yet to be transferred for a given block.
14-5, holds the address to which the DMA controller sends data.
28
12
28
12
IPSBAR + 0x00_0104 (DMA0); IPSBAR + 0x00_0114 (DMA1);
IPSBAR + 0x00_0108 (DMA0); IPSBAR + 0x00_0118 (DMA1);
0
0
0
0
IPSBAR + 0x00_0124 (DMA2); IPSBAR + 0x00_0134 (DMA3)
IPSBAR + 0x00_0128 (DMA2); IPSBAR + 0x00_0138 (DMA3)
DSR
27
27
11
11
0
0
0
0
MCF5235 Reference Manual, Rev. 2
26
10
26
10
0
0
0
0
25
25
0
0
0
0
9
9
NOTE
24
24
0
0
0
0
8
8
DAR
DAR
BCR
23
23
0
0
0
0
7
7
22
22
0
6
0
0
6
0
21
21
0
0
0
0
5
5
20
20
0
0
0
0
4
4
BCR
Memory Map/Register Definition
19
19
0
0
0
0
3
3
18
18
0
0
0
0
2
2
17
17
0
0
0
0
1
1
16
16
0
0
0
0
0
0
14-7