MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 661

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

32.4.8
The TDR, shown in
corresponds with the ABHR/ABLR/AATR, PBR/PBMR, and DBR/DBMR registers within the
debug module. The TDR controls the actions taken under the defined conditions. Breakpoint logic
may be configured as a one- or two-level trigger. TDR[31–16] define the second-level trigger and
bits 15–0 define the first-level trigger.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
Table 32-15
Freescale Semiconductor
DRc[4–0]
Reset
Reset
31–0
Bits
W
W
R
R
31
15
0
0
0
Trigger Definition Register (TDR)
TRC
describes TDR fields.
The debug module has no hardware interlocks, so to prevent spurious
breakpoint triggers while the breakpoint registers are being loaded,
disable TDR (by clearing TDR[29,13])before defining triggers.
30
14
0
0
0
Name
Mask
EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU
EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU
Table
29
13
0
0
Figure 32-11. Trigger Definition Register (TDR)
PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be
compared to the appropriate PC bit. Set PBMR bits cause PBR bits to be ignored.
28
12
32-11, configures the operation of the hardware breakpoint logic that
0
0
Table 32-14. PBMR Field Descriptions
27
11
0
0
MCF5235 Reference Manual, Rev. 2
26
10
0
0
25
0
0
9
NOTE
24
0
8
0
Second-Level Trigger
0x07
First-Level Trigger
Description
23
0
0
7
22
0
6
0
DI
21
DI
0
0
5
EAI
EAI
20
0
0
4
Memory Map/Register Definition
EAR EAL EPC
EAR EAL EPC
19
0
0
3
18
0
0
2
17
0
0
1
PCI
PCI
32-17
16
0
0
0