MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 431

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Freescale Semiconductor
31–28
24–21
20–16
15–11
Bits
8–7
31
27
26
25
10
9
SCMMISEN
SCMMISF
SCMSIZE
MGEA
Name
GEC
ILFA
—
—
—
—
—
Table 20-3. ETPU_MCR Bit Field Descriptions
Global exception clear. Negates global exception request and clears global exception
status bits MGEA, ILFA, and SCMMISF. A read will always return 0. Writes have the
following effect:
0 Keep global exception request and status bits ILFA, MGEA, and SCMMISF as is.
1 Negate global exception, clear status bits ILFA, MGEA, and SCMMISF.
GEC works the same way with either one or both engines in stop mode.
Reserved.
Microcode global exception. Indicates that a global exception was asserted by microcode
executed on the engine. The determination of the reason why the global exception was
asserted is application dependent: it can be coded in an SDM status parameter, for
instance. This bit is cleared by writing 1 to GEC.
0 No microcode-requested global exception pending.
1 Global exception requested by microcode is pending.
Reserved.
Illegal instruction flag. Set by the microengine to indicate that an illegal instruction was
decoded in the engine. This bit is cleared by host writing 1 to GEC. For more information
about illegal instructions, see the eTPU User’s Manual.
0 Illegal Instruction not detected.
1 Illegal Instruction detected.
Reserved.
SCM size. Holds the number of 2 Kbyte SCM Blocks minus 1. This value is fixed at 00010
for the MCF5235 to indicate that the SCM is 6 Kbytes.
Reserved.
SCM MISC Flag. Set by the SCM MISC (Multiple Input Signature Calculator) logic to
indicate that the calculated signature does not match the expected value, at the end of a
MISC iteration. The SCMMISF bit is not affected by eTPU internal soft reset. For more
details, refer to the eTPU User’s Manual for more details.
0 Signature mismatch not detected.
1 MISC has read entire SCM array and the expected signature in ETPU_MISCCMPR
This bit is automatically cleared when SCMMISEN changes from 0 to 1, or when global
exception is cleared by writing 1 to GEC.
SCM MISC enable. Used for enabling/disabling the operation of the MISC logic.
SCMMISEN is readable and writable at any time. The MISC logic will only operate when
this bit is set to 1. When the bit is reset the MISC address counter is set to the initial SCM
address. When enabled, the MISC will continuously cycle through the SCM addresses,
reading each and calculating a CRC. In order to save power, the MISC can be disabled by
clearing the SCMMISEN bit. The SCMMISEN bit is not affected by eTPU internal soft reset.
For more details, refer to the eTPU User’s Manual.
0 MISC operation disabled. The MISC logic is reset to its initial state.
1 MISC operation enabled. (Toggling to 1 clears the SCMMISF bit)
SCMMISEN is cleared automatically when MISC logic detects an error; that is, when
SCMMISF transitions from 0 to 1, disabling the MISC operation.
Reserved.
does not match the value calculated.
MCF5235 Reference Manual, Rev. 2
Description
Memory Map/Register Definition
20-17