MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 273

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

13.2.1.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)
The INTFRCHn and INTFRCLn registers are each 32 bits in size and provide a mechanism to
allow software generation of interrupts for each possible source for functional or debug purposes.
The system design may reserve one or more sources to allow software to self-schedule interrupts
by forcing one or more of these bits (1 = force request, 0 = negate request) in the appropriate
INTFRCn register. The assertion of an interrupt request via the INTFRCn register is not affected
by the interrupt mask register. The INTFRCn register is cleared by reset.
Freescale Semiconductor
Address
Reset
Reset
31–1
Bits
0
W
W
R
R
31
15
1
1
INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRLn bit
MASKALL Mask all interrupts. Setting this bit will force the other 63 bits of the IMRHn and IMRLn to
Name
30
14
1
1
Figure 13-4. Interrupt Mask Register Low (IMRLn)
29
13
1
1
determines whether an interrupt condition can generate an interrupt. The corresponding
IPRLn bit reflects the state of the interrupt signal even if the corresponding IMRLn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
ones, disabling all interrupt sources, and providing a global mask-all capability.
IPSBAR + 0x00_0C0C (INTC0), IPSBAR + 0x00_0D0C (INTC1)
28
12
1
1
Table 13-7. IMRLn Field Descriptions
27
11
1
1
MCF5235 Reference Manual, Rev. 2
26
10
1
1
25
1
1
9
INT_MASK
INT_MASK
24
1
1
8
23
1
1
7
Description
22
1
1
6
21
1
5
1
20
1
1
4
Memory Map/Register Definition
19
1
1
3
18
1
1
2
17
1
1
1
MASK
ALL
16
1
1
0
13-9