MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 561

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Similarly, the receive DMA request signal is asserted when the FFULL/RxRDY (FIFO full or
receive ready) flag in the Interrupt Status Register, UISR[FFULL/RxRDY], is set. When the
receive DMA request signal is asserted, the DMA can initiate a data move, reading the appropriate
characters from the UART Receive Buffer (URBn) and storing them in memory. This allows the
DMA channel to stream data from the UART receive buffer into memory without processor
intervention. Once the entire message has been moved from the UART, the DMA would typically
generate an end-of-data-transfer interrupt request to the CPU. The resulting interrupt service
routine (ISR) should query the UART programming model to determine the end-of-transmission
status. In typical applications, the receive DMA request should be configured to use RxRDY
directly (and not FFULL) to remove any complications related to retrieving the final characters
from the FIFO buffer.
The implementation described in this section allows independent DMA processing of transmit and
receive data while still supporting interrupt notification to the processor for CTS change-of-state
and “delta break” error handling.
To configure the UART for DMA requests:
Table 26-14
Freescale Semiconductor
1. Initialize the DMAREQC in the SCM to map the desired UART DMA requests to the
2. Disable interrupts using the UIMR register. The appropriate UIMR bits must be cleared
3. Configure the GPACR and appropriate PACR registers located in the SCM for DMA
4. Initialize the DMA channel. The DMA should be configured for cycle steal mode and a
desired DMA channels. For example; setting DMAREQC[7:4] to 1000 maps UART0
receive DMA requests to DMA channel 1; setting DMAREQC[11:8] to 1101 maps UART1
transmit DMA requests to DMA channel 2; and so on. It is possible to independently map
transmit based and receive based UART DMA requests in the DMAREQC.
so that interrupt requests are disabled for those conditions for which a DMA request is
desired. For example; to generate transmit DMA requests from UART1, then
UIMR1[TxRDY] should be cleared. This will prevent TxRDY from generating an
interrupt request while a transmit DMA request is generated.
access to IPSBAR space.
source and destination size of one byte. This will cause a single byte to be transferred for
each UART DMA request.
shows the DMA requests.
Register
UISRn
UISRn
Table 26-14. UART DMA Requests
Bit
1
0
MCF5235 Reference Manual, Rev. 2
Receive DMA request
Transmit DMA request
DMA Request
Functional Description
26-29