MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 658

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Debug Support
32-14
23-22
21-20
19-16
Bits
28
27
ETPBKPT
CFBKPT
ETPGO
Name
ETPB
IDE
eTPU Breakpoint. This read-only status bit indicates if the eTPU is currently at a
breakpoint.
0 eTPU is not halted
1 eTPU is halted
Integrated Debug Enable. This read-only configuration enable is loaded with the logical
complement of the chip input JTAG_EN at reset. The state of this bit can only be changed
by a system reset.
0 The integrated ColdFire/eTPU debug functionality is completely disabled. The debug
functionality allows the use of the shared JTAG/BDM pins in JTAG mode only for eTPU
debug.
1 The integrated ColdFire/eTPU debug functionality is enabled. The shared JTAG/BDM
pins operate in ColdFire mode to support the integrated debug functionality.
ColdFire Breakpoint Enables. This 2-bit field enables the occurrence of specific debug
events to breakpoint the ColdFire processor core.
1x enable eTPU debug event
x1 enable BKPT chip input signal
Note: XCSR[22] is loaded with the logical complement of the chip input JTAG_EN at reset,
but can be changed by any write to the XCSR.
eTPU Go. This 2-bit field defines when the the eTPU is allowed to resume execution from
breakpoints (external debug requests). All cross-triggered breakpoint events are treated as
an external debug request to the eTPU.
Once the eTPU has recognized a breakpoint and is halted from an external debug request,
this 2-bit field controls the ability of the eTPU to resume normal execution:
00 The operation of the eTPU is unaffected.
1x Resume normal execution in the eTPU when a BDM Go command is processed by the
x1 Setting this bit immediately resumes normal execution within the eTPU while the core
eTPU Breakpoint Enables. This 4-bit field enables the occurrence of specific debug events
to generate an external breakpoint to the eTPU. The combination of the specific debug
events, qualified by the appropriate ETPBKPT enable, are logically summed together and
force the eTPU into debug mode via a special debug interrupt.
ETPBKPT[3] = enable ColdFire Trigger 2
ETPBKPT[2] = enable ColdFire Trigger 1
ETPBKPT[1] = enable CORE_IS_HALTED
ETPBKPT[0] = enable BKPT chip input signal
Where the ColdFire Triggers (1,2) are the first and second-level debug address/data/PC
breakpoint registers. The firing of a ColdFire trigger can be programmed to generate a
special debug interrupt.
The detection of a properly-enabled debug event sets a control state which sources a
special debug interrupt to the eTPU. The control state remains asserted until the
appropriate ETPGO exit condition occurs.
ColdFire debug module. The Go command is used to restart the ColdFire core.
is still stopped. Since the ETPGO[0] control field resets after a single cycle, it is always
read as a logical zero.
Table 32-9. XCSR Field Descriptions
MCF5235 Reference Manual, Rev. 2
Description
Freescale Semiconductor