MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 438
![MOD5234 10/100 ETHERNET MODULE](/photos/28/91/289101/mod-100ir_sml.jpg)
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
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Enhanced Time Processing Unit (eTPU)
20-24
31–29
28–27
Bits
26
TCR2CTL
TCRCF
Name
—
Table 20-7. ETPU_TBCR Field Descriptions
TCR2 clock/gate control. Part of the TCR2 clocking system. These bits determine the
clock source for TCR2. TCR2 can count on any detected edge of the TCRCLK signal
or use it for gating internal bus clock divided by 8. After reset, TCRCLK signal rising
edge is selected. TCR2 can also be clocked by the internal bus clock divided by 8.
Refer to the eTPU User’s Manual for more information. TCR2 clock sources are listed
in the following table.
TCRCLK signal filter control. Controls the TCRCLK digital filter determining whether
the TCRCLK signal input (after a synchronizer) is filtered with the same filter clock as
the channel input signals or uses the internal bus clock divided by 2, and also whether
the TCRCLK digital filter works in integrator mode or two sample mode. The following
table describes TCRCLK filter clock/mode.
For more information, refer to two sections in the eTPU User’s Manual.
Reserved.
TCR2CTL
000
001
010
011
100
101
110
111
TCRCF
MCF5235 Reference Manual, Rev. 2
00
01
10
11
Gated DIV8 clock (internal bus clock / 8). When the
external TCRCLK signal is low, the DIV8 clock is
blocked, preventing it from incrementing TCR2.
When the external TCRCLK signal is high, TCR2 is
incremented at the frequency of the internal bus
clock divided by 8.
Rise transition on TCRCLK signal increments
TCR2.
Fall transition on TCRCLK signal increments TCR2. Falling Edge
Rise or fall transition on TCRCLK signal increments
TCR2.
Reserved
internal bus clock divided by 2
internal bus clock divided by 2
filter clock of the channels
filter clock of the channels
Filter Input
TCR2 Clock
Description
Filter Mode
two sample
two sample
integration
integration
Freescale Semiconductor
Not Used
Rising Edge
Rising or
Falling Edge
Not Used
Angle Tooth
Detection
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