MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 283

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

13.3
The interrupt controllers have a fixed priority, where INTC0 has the highest priority, and INTC1
has the lowest priority. If both interrupt controllers have active interrupts at the same level and
priority, then the INTC0 interrupt will be serviced first. If INTC1 has an active interrupt that has
a higher level or priority than the highest INTC0 interrupt, then the INTC1 interrupt will be
serviced first.
13.4
The System Control Module (SCM) contains an 8-bit low-power interrupt control register
(LPICR) used explicitly for controlling the low-power stop mode. This register must explicitly be
programmed by software to enter low-power mode.
Each interrupt controller provides a special combinatorial logic path to provide a special wake-up
signal to exit from the low-power stop mode. This special mode of operation works as follows:
Freescale Semiconductor
• First, LPICR[XLPM_IPL] is loaded with the mask level that will be specified while the
• Second, the processor executes a STOP instruction which places it in stop mode. Once the
Figure 13-10. Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
core is in stop mode. LPICR[ENBSTOP] must be set to enable this mode of operation.
processor is stopped, each interrupt controller enables a special logic path which evaluates
the incoming interrupt sources in a purely combinatorial path; that is, there are no clocked
Bits
7–0
Prioritization Between Interrupt Controllers
Low-Power Wakeup Operation
The wakeup mask level taken from LPICR[XLPM_IPL] is adjusted
by hardware to allow a level 7 IRQ to generate a wakeup. That is, the
wakeup mask value used by the interrupt controller must be in the
range of 0–6.
Table 13-15. SWIACK and L1IACK-L7IACK Field Descriptions
VECTOR
Name
Address
Reset
W
R
Vector number. A read from the SWIACK register returns the vector number associated
with the highest level, highest priority unmasked interrupt source. A read from one of the
LnACK registers returns the highest priority unmasked interrupt source within the level.
0
7
See
MCF5235 Reference Manual, Rev. 2
0
6
Table 13-2
0
5
NOTE
and
0
4
VECTOR
Table 13-3
Description
0
3
for register offsets
2
0
Prioritization Between Interrupt Controllers
0
1
0
0
13-19