MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 505

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

synchronization delay is between two and three system clocks. The corresponding DTMRn[CLK]
selects the clock input source. A programmable prescaler divides the clock input by values from
1 to 256. The prescaler output is an input to the 32-bit counter, DTCNn.
24.2.2 Capture Mode
Each DMA timer has a 32-bit timer capture register (DTCRn) that latches the counter value when
the corresponding input capture edge detector senses a defined DTINn transition. The capture edge
bits (DTMRn[CE]) select the type of transition that triggers the capture and sets the timer event
register capture event bit, DTERn[CAP]. If DTERn[CAP] is set and DTXMRn[DMAEN] is one,
a DMA request is asserted. If DTERn[CAP] is set and DTXMRn[DMAEN] is zero, an interrupt
is asserted.
24.2.3 Reference Compare
Each DMA timer can be configured to count up to a reference value, at which point DTERn[REF]
is set. If DTMRn[ORRI] is one and DTXMRn[DMAEN] is zero, an interrupt is asserted. If
DTMRn[ORRI] is one and DTXMRn[DMAEN] is one, a DMA request is asserted. If the free
run/restart bit DTMRn[FRR] is set, a new count starts. If it is clear, the timer keeps running.
24.2.4 Output Mode
When a timer reaches the reference value selected by DTRR, it can send an output signal on
DTOUTn. DTOUTn can be an active-low pulse or a toggle of the current output as selected by the
DTMRn[OM] bit.
24.2.5 Memory Map
The timer module registers, shown in
Freescale Semiconductor
0x00_040C
0x00_0400
0x00_0404
0x00_0408
0x00_0440
IPSBAR
Offset
DMA Timer0 Mode Register (DTMR0)
DMA Timer1 Mode Register (DTMR1)
[31:24]
Table 24-1. DMA Timer Module Memory Map
MCF5235 Reference Manual, Rev. 2
DMA Timer0 Reference Register (DTRR0)
Table
DMA Timer0 Capture Register (DTCR0)
DMA Timer0 Counter Register (DTCN0)
[23:16]
24-1, can be modified at any time.
Register (DTXMR0)
Register (DTXMR1)
Extended Mode
Extended Mode
DMA Timer0
DMA Timer1
[15:8]
DMA Timer0 Event
DMA Timer1 Event
Memory Map/Register Definition
Register (DTER0)
Register (DTER1)
[7:0]
24-3