MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 750
![MOD5234 10/100 ETHERNET MODULE](/photos/28/91/289101/mod-100ir_sml.jpg)
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
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Signals
Index-10
registers
self-refresh 18-18
signals
block diagram 2-2
bus 17-1
CCM
chip select module
clock module
debug
eTPU
external boot mode 2-17
FlexCAN 21-6
JTAG
low-power modes 8-6
synchronous
address and control 0–1 (DACRn) 18-7
control (DCR) 18-5
mask (DMRn) 18-9
mode register
summary 18-4
CLKMOD1–0 9-2
RCON 9-2
byte strobes (BS3–0) 16-2
chip select (CS7–0) 16-1
output enable (OE) 16-1
CLKMOD1–0 7-7
CLKOUT 7-7
EXTAL 7-7
RSTOUT 7-7
XTAL 7-7
breakpoint (BKPT) 32-3
debug data (DDATA3–0) 32-3
development serial clock (DSCLK) 32-3
development serial input (DSI) 32-3
development serial output (DSO) 32-3
processor status (PST3–0) 32-3
channel (TPUCH31–0) 20-13
channel output disable (LTPUODIS,
time base clock (TCRCLK) 20-13
JTAG_EN 31-3
TCLK 31-4
test data input/development serial input
test data output/development serial output
test mode select/breakpoint (TMS/BKPT) 31-4
address multiplexing 18-10
initialization 18-25
settings 18-20
UTPUODIS) 20-13
(TDI/DSI) 31-4
(TDO/DSO) 31-5
MCF5235 Reference Manual, Rev. 2
SKHA
SRAM
Stack pointer 3-3
SYNC_SEG 21-31
System clock 7-15
T
TAP controller 31-7
Time Stamp 21-24
Time stamp 21-30
Timers
QSPI
reset controller
SDRAM controller
summary 2-3
FIFO 30-14
logic 30-17
memory map 30-6
operation
registers
cache, interaction 5-3
initialization 6-4
operation
power management 6-5
registers
DTIM
test reset/development serial clock
summary 25-2
RESET 10-2
RSTOUT 10-2
summary 18-4
AES 30-3
CBC 30-4
context switch 30-20
CTR 30-5
DES, 3DES 30-2
ECB 30-3
general 30-19
command (SKCMR) 30-9
context (SKCRn) 30-15
control (SKCR) 30-8
data size (SKDSR) 30-13
error status (SKESR) 30-11
error status mask (SKESMR) 30-12
key data (SKKDRn) 30-14
key size (SKKSR) 30-13
mode (SKMR) 30-7
status (SKSR) 30-10
low-power modes 8-6
RAMBAR 6-2
capture mode 24-3
(TRST/DSCLK) 31-4
,
30-17
,
3-7
,
21-25
Freescale Semiconductor
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