MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 15

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

16.1
16.1.1
16.2
16.2.1
16.2.2
16.2.3
16.3
16.3.1
16.3.1.1
16.3.2
16.3.2.1
16.4
16.4.1
16.4.1.1
16.4.1.2
16.4.1.3
16.5
17.1
17.1.1
17.2
17.3
17.4
17.5
17.5.1
17.5.2
17.5.3
17.5.4
17.5.5
17.5.6
17.5.7
17.5.7.1
17.5.7.2
17.5.7.3
17.6
Freescale Semiconductor
Paragraph
Number
Introduction ................................................................................................................... 16-1
External Signal Description .......................................................................................... 16-1
Chip Select Operation ................................................................................................... 16-3
Memory Map/Register Definition ................................................................................ 16-6
Code Example ............................................................................................................. 16-11
Introduction ................................................................................................................... 17-1
Bus and Control Signals ............................................................................................... 17-1
Bus Characteristics ....................................................................................................... 17-2
Bus Errors ..................................................................................................................... 17-3
Data Transfer Operation ............................................................................................... 17-3
Secondary Wait State Operation ................................................................................. 17-15
Overview ................................................................................................................... 16-1
Chip Selects (CS[7:0]) .............................................................................................. 16-1
Output Enable (OE) .................................................................................................. 16-1
Byte Strobes (BS[3:0]) .............................................................................................. 16-2
General Chip Select Operation ................................................................................. 16-3
Enhanced Wait State Operation ................................................................................ 16-4
Chip Select Module Registers ................................................................................... 16-7
Features ..................................................................................................................... 17-1
Bus Cycle Execution ................................................................................................. 17-4
Data Transfer Cycle States ....................................................................................... 17-5
Read Cycle ................................................................................................................ 17-7
Write Cycle ............................................................................................................... 17-8
Fast Termination Cycles ........................................................................................... 17-9
Back-to-Back Bus Cycles ....................................................................................... 17-10
Burst Cycles ............................................................................................................ 17-11
8-, 16-, and 32-Bit Port Sizing .............................................................................. 16-4
External Boot Chip Select Operation ................................................................... 16-6
Chip Select Address Registers (CSAR0–CSAR7) ............................................... 16-7
Chip Select Mask Registers (CSMR0–CSMR7) .................................................. 16-8
Chip Select Control Registers (CSCR0–CSCR7) ................................................. 16-9
Line Transfers ..................................................................................................... 17-12
Line Read Bus Cycles ......................................................................................... 17-12
Line Write Bus Cycles ........................................................................................ 17-14
External Interface Module (EIM)
MCF5235 Reference Manual, Rev. 2
Chip Select Module
Contents
Chapter 16
Chapter 17
Title
Number
Page
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