MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 340

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Synchronous DRAM Controller Module
The DRAM controller’s major components are as follows:
18-2
• DRAM address and control registers (DACR0 and DACR1): The DRAM controller
• Control logic and state machine: Generates all SDRAM signals, taking hit information and
• Hit logic: Compares address and attribute signals of a current SDRAM bus cycle to both
• Address multiplexing: Multiplexes addresses to allow column and row addresses to share
• Data Generation: Controls the data input and data output transmission between the
Internal
Q[31:0] internal
A[31:0]
D[31:0] internal
Bus
consists of two configuration register units, one for each supported memory block. DACR0
is accessed at IPSBAR + 0x00_0048; DACR1 is accessed at IPSBAR + 0x00_0050. The
register information is passed on to the hit logic.
bus-cycle characteristic data from the block logic in order to generate SDRAM accesses.
Handles refresh requests from the refresh counter.
— DRAM control register (DCR): Contains data to control refresh operation of the DRAM
— Refresh counter: Determines when refresh should occur; controlled by the value of
DACRs to determine if an SDRAM block is being accessed. Hits are passed to the control
logic along with characteristics of the bus cycle to be generated.
pins. This allows glueless interface to SDRAMs.
on-platform and off-platform data buses.
controller. Both memory blocks are refreshed concurrently as controlled by DCR[RC].
DCR[RC]. It generates a refresh request to the control block.
DRAM Controller Module
Figure 18-1. Synchronous DRAM Controller Block Diagram
DRAM Address/Control Register 0
DRAM Address/Control Register 1
Memory Block 0 Hit Logic
Memory Block 1 Hit Logic
(DACR0)
(DACR1)
MCF5235 Reference Manual, Rev. 2
Refresh Counter
Register (DCR)
DRAM Control
State Machine
Control Logic
Multiplexing
Generation
Address
Data
and
D[31:0]
A[23:0]
Q[31:0]
SD_CS[1:0]
SD_SCAS
SD_SRAS
SD_CKE
SD_WE
BS[3:0]
OE
Freescale Semiconductor