MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 326
![MOD5234 10/100 ETHERNET MODULE](/photos/28/91/289101/mod-100ir_sml.jpg)
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
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- Download datasheet (13Mb)
External Interface Module (EIM)
Figure 17-2
transfers if a longword is transferred for three port sizes. For example, an 8-bit memory should be
connected to D[31:24] (BS3). A longword transfer takes four transfers on D[31:24], starting with
the MSB and going to the LSB.
The timing relationship of chip selects (CS[7:0]), byte selects (BS[3:0]), and output enable (OE)
with respect to CLKOUT is similar in that all transitions occur during the low phase of CLKOUT.
However, due to differences in on-chip signal routing, signals may not assert simultaneously.
17.5.1 Bus Cycle Execution
When a bus cycle is initiated, the MCF5235 first compares the address of that bus cycle with the
base address and mask configurations programmed for chip selects 0–7 (configured in
CSCR0–CSCR7) and DRAM block 0 and 1 address and control registers (configured in DACR0
and DACR1). If the driven address compares with one of the programmed chip selects or DRAM
blocks, the appropriate chip select is asserted or the DRAM block is selected using the
specifications programmed by the user in the respective configuration register. Otherwise, the
following occurs:
17-4
• If the address and attributes do not match in CSCR or DACR, the MCF5235 runs an
external burst-inhibited bus cycle with a default of external termination on a 32-bit port.
shows the byte lanes that external memory should be connected to and the sequential
Figure 17-2. Connections for External Memory Port Sizes
Figure 17-3. Chip-Select Module Output Timing Diagram
CLKOUT
CS[7:0]
BS[3:0]
OE
Byte Enable
32-Bit Port
16-Bit Port
Processor
Data Bus
8-Bit Port
External
Memory
Memory
Memory
MCF5235 Reference Manual, Rev. 2
D[31:24]
Byte 0
Byte 0
Byte 2
Byte 0
Byte 1
Byte 2
Byte 3
BS3
D[23:16]
Byte 1
Byte 1
Byte 3
BS2
indeterminate values
Driven with
indeterminate values
D[15:8]
Byte 2
BS1
Driven with
Byte 3
D[7:0]
BS0
Freescale Semiconductor
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