MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 458
![MOD5234 10/100 ETHERNET MODULE](/photos/28/91/289101/mod-100ir_sml.jpg)
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
- Current page: 458 of 754
- Download datasheet (13Mb)
FlexCAN
21.1.3 Modes of Operation
21.1.3.1 Normal Mode
In normal mode, the module operates receiving and/or transmitting message frames, errors are
handled normally, and all the CAN protocol functions are enabled. User and supervisor modes
differ in the access to some restricted control registers.
21.1.3.2 Freeze Mode
Freeze mode is entered by:
Once entry into freeze mode is requested, the FlexCAN waits until an intermission or idle
condition exists on the CAN bus, or until the FlexCAN enters the error passive or bus off state.
Once one of these conditions exists, the FlexCAN waits for the completion of all internal activity
such as arbitration, matching, move-in, and move-out. When this happens, the following events
occur:
After engaging one of the mechanisms to place the FlexCAN in freeze mode, the user must wait
for the FRZACK bit to be set before accessing any other registers in the FlexCAN, otherwise
unpredictable operation may occur. In freeze mode, all memory mapped registers are accessible.
21-4
• Global network time, synchronized by a specific message
• Programmable I/O modes
• Maskable interrupts
• Independent of the transmission medium (an external transceiver is assumed)
• Open network architecture
• Multimaster bus
• High immunity to EMI
• Short latency time due to an arbitration scheme for high-priority messages
• Setting CANMCRn[FRZ], and
• Setting CANMCRn[HALT], or by asserting the BKPT line.
• The FlexCAN stops transmitting/receiving frames.
• The prescaler is disabled, thus halting all CAN bus communication.
• The FlexCAN ignores its Rx pins and drives its Tx pins as recessive.
• The FlexCAN loses synchronization with the CAN bus and the NOTRDY and FRZACK
• The CPU is allowed to read and write the error counter registers (in other modes they are
bits in CANMCRn are set.
read-only).
MCF5235 Reference Manual, Rev. 2
Freescale Semiconductor
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