MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 287

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

14.2
The DMA module can move data within system memory (including memory and peripheral
devices) with minimal processor intervention, greatly improving overall system performance. The
DMA module consists of four independent, functionally equivalent channels, so references to
DMA in this chapter apply to any of the channels. It is not possible to implicitly address all four
channels at once.
The processor generates DMA requests internally by setting DCR[START]; the UART modules
and DMA timers can generate a DMA request by asserting internal DREQ signals. The eTPU
DMA request is considered an external request on the MCF5235. Therefore the user must setup
the DMA channel for an external request when wanting the eTPU to trigger the DMA module.
The processor can program bus bandwidth for each channel. The channels support cycle-steal and
continuous transfer modes; see
Modes).”
The DMA controller supports dual-address transfers. The DMA channels support up to 32 data
bits.
Freescale Semiconductor
• Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer
• Continuous-mode or cycle-steal transfers
• Independent transfer widths for source and destination
• Independent source and destination address registers
• Modulo addressing on source and destination addresses
• Automatic channel linking
• Dual-address transfers—A dual-address transfer consists of a read followed by a write and
is initiated by an internal request using the START bit or by asserting DREQn. Two types
of transfer can occur: a read from a source device or a write to a destination device. See
Figure 14-2
DMA Transfer Overview
for more information.
Figure 14-2. Dual-Address Transfer
Section 14.4.1, “Transfer Requests (Cycle-Steal and Continuous
DMA
DMA
MCF5235 Reference Manual, Rev. 2
Control and Data
Control and Data
Peripheral
Peripheral
Memory/
Memory/
DMA Transfer Overview
14-3