MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 424

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Enhanced Time Processing Unit (eTPU)
20-10
• Event-triggered RISC processor (microengine):
• Resource sharing features resolve channel contention for common use of channel registers,
— The first time base may be clocked by the internal bus clock with programmable
— The first time base can also be clocked by an external signal with programmable
— The second time base may be clocked by an external signal with programmable
— The second time base counter can work as an angle counter, enabling angle based
— The second time base can alternatively be used as a pulse accumulator gated by an
— 2 stage pipeline implementation (fetch and execution), with separate instruction
— Two system clock microcycle fixed-length instruction execution for the ALU.
— 6 Kbytes of shared code memory (SCM).
— 1.5 Kbytes of shared data memory (SDM).
— Instruction set with embedded channel support, including specialized channel control
— Channel-oriented addressing: channel-bound address mode with host configured
— Channel-bound data address space of up to 128 32-bit parameters (512 bytes).
— Global parameter address mode allows access to common channel data of up to 256
— Support for indirect and stacked data access schemes.
— Parallel execution of: data access, ALU, channel control and flow control
— 32-bit microengine registers and 24-bit resolution ALU, with 1 microcycle addition and
— Additional 24-bit multiply/MAC/divide unit which supports all signed/unsigned/
memory and microengine time:
prescaler division from 2 to 512 (in steps of 2), or by the output of the second time base
prescaler.
prescaler division of 1 to 256.
prescaler division from 1 to 64 or by the internal bus clock divided by 8.
applications to match angle instead of time.
external signal.
memory (SCM) and data memory (SDM).
subinstructions and conditional branching on channel-specific flags.
channel base address allows the same function to operate independently on different
channels.
32-bit parameters (1024 bytes).
subinstructions in selected combinations.
subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte
operands: single bit manipulation, shift operations, sign extension and conditional
execution.
multiply/MAC combinations, and unsigned 24-bit divide. The MAC/divide unit works
in parallel with the regular microcode commands.
MCF5235 Reference Manual, Rev. 2
Freescale Semiconductor