MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 70

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Signal Descriptions
2.3.8 Ethernet Module (FEC) Signals
The following signals are used by the Ethernet module for data and clock signals. Some of these
signals are muxed with eTPU channels on the MCF5235 and dedicated on the other members of
the family that have an Ethernet Module.
2-12
TCRCLK
TPUCH[31:0]
LTPUODIS
UTPUDIS
Management Data
Management Data
Clock
Transmit Clock
Transmit Enable
Transmit Data 0
Collision
Receive Clock
Receive Data Valid
Signal Name
Signal Name
TCRCLK
TPUCH[31:0] Channel pins for the eTPU module. They can also be configured for
LTPUODIS
UTPUDIS
EMDIO
EMDC
ETXCLK
ETXEN
ETXD0
ECOL
ERXCLK
ERXDV
Abbreviation
Abbreviation
Table 2-9. Ethernet Module (FEC) Signals
MCF5235 Reference Manual, Rev. 2
Disables eTPU outputs on the upper 16 channels of the eTPU.
Asserted upon detection of a collision and remains asserted while the
Used to clock the TCR1/2 counters or gate the TCR2 clock.
Ethernet controller functionality. See table
Section 2.3.8, “Ethernet Module (FEC)
Disables eTPU outputs on the lower 16 channels of the eTPU.
Transfers control information between the external PHY and the
media-access controller. Data is synchronous to EMDC. Applies to MII
mode operation. This signal is an input after reset. When the FEC is
operated in 10Mbps 7-wire interface mode, this signal should be
connected to VSS.
In Ethernet mode, EMDC is an output clock which provides a timing
reference to the PHY for data transfers on the EMDIO signal. Applies
to MII mode operation.
Input clock which provides a timing reference for ETXEN, ETXD[3:0]
and ETXER
Indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the
first ETXCLK following the final nibble of the frame.
ETXD0 is the serial output Ethernet data and is only valid during the
assertion of ETXEN. This signal is used for 10-Mbps Ethernet data. It
is also used for MII mode data in conjunction with ETXD[3:1].
collision persists. This signal is not defined for full-duplex mode.
Provides a timing reference for ERXDV, ERXD[3:0], and ERXER.
Asserting the receive data valid (ERXDV) input indicates that the PHY
has valid nibbles present on the MII. ERXDV should remain asserted
from the first recovered nibble of the frame through to the last nibble.
Assertion of ERXDV must start no later than the SFD and exclude any
EOF.
Table 2-8. eTPU Signals
Function
Function
Signals,” for details.
Table 2-1
and
Freescale Semiconductor
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I