MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 321

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

16.5 Code Example
CSAR0 EQU IPSBARx+0x080 ;Chip select 0 address register
CSMR0 EQU IPSBARx+0x084 ;Chip select 0 mask register
CSCR0 EQU IPSBARx+0x08A ;Chip select 0 control register
CSAR1 EQU IPSBARx+0x08C ;Chip select 1 address register
CSMR1 EQU IPSBARx+0x090 ;Chip select 1 mask register
CSCR1 EQU IPSBARx+0x096 ;Chip select 1 control register
CSAR2 EQU IPSBARx+0x098 ;Chip select 2 address register
CSMR2 EQU IPSBARx+0x09C ;Chip select 2 mask register
CSCR2 EQU IPSBARx+0x0A2 ;Chip select 2 control register
CSAR3 EQU IPSBARx+0x0A4 ;Chip select 3 address register
CSMR3 EQU IPSBARx+0x0A8 ;Chip select 3 mask register
CSCR3 EQU IPSBARx+0x0AE ;Chip select 3 control register
CSAR4 EQU IPSBARx+0x0B0 ;Chip select 4 address register
CSAR4 EQU IPSBARx+0x0B4 ;Chip select 4 mask register
CSMR4 EQU IPSBARx+0x0BA ;Chip select 4 control register
CSAR5 EQU IPSBARx+0x0BC ;Chip select 5 address register
CSMR5 EQU IPSBARx+0x0C0 ;Chip select 5 mask register
CSCR5 EQU IPSBARx+0x0C6 ;Chip select 5 control register
CSAR6 EQU IPSBARx+0x0C8 ;Chip select 6 address register
CSMR6 EQU IPSBARx+0x0CC ;Chip select 6 mask register
CSCR6 EQU IPSBARx+0x0D2 ;Chip select 6 control register
Freescale Semiconductor
Bits
2–0
3
SWWS
BSTW
Name
Table 16-7. CSCRn Field Descriptions (Continued)
Burst write enable. Specifies whether burst writes are used for memory associated with
each CSn.
0 Break data larger than the specified port size into individual port-sized, non-burst writes.
1 Enables burst write of data larger than the specified port size, including longword writes
Secondary write wait states. The number of wait states applied to all writes after the initial
one if properly enabled (SWWS is non-zero and CSCR[AA] = 1). The default for this field is
Operation,”
000 Secondary write wait states are disabled. Use CSCR[IWS] for all accesses.
001 0 wait states for the secondary write accesses
010 1 wait state for the secondary write accesses
011 2 wait states for the secondary write accesses
100 3 wait states for the secondary write accesses
101 4 wait states for the secondary write accesses
110 5 wait states for the secondary write accesses
111 6 wait states for the secondary write accesses
secondary write wait states disabled. See
For example, a longword write to an 8-bit port takes four byte writes.
to 8 and 16-bit ports, word writes to 8-bit ports and line writes to 8-, 16-, and 32-bit ports.
for timing diagrams. This field is encoded as:
MCF5235 Reference Manual, Rev. 2
Description
Section 16.3.2, “Enhanced Wait State
Code Example
16-11