MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 481

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

21.4.5 Message Buffer Handling
In order to maintain data coherency and FlexCAN proper operation, the CPU must obey the rules
described in
of CPU accessing a MB structure within FlexCAN other than those specified may cause FlexCAN
to behave in an unpredictable way.
21.4.5.1 Serial Message Buffers (SMBs)
To allow double buffering of messages, the FlexCAN has two shadow buffers called serial
message buffers. These two buffers are used by the FlexCAN for buffering both received messages
and messages to be transmitted. Only one SMB is active at a time, and its function depends upon
the operation of the FlexCAN at that time. At no time does the user have access to or visibility of
these two buffers.
21.4.5.2 Message Buffer Deactivation
If the CPU wants to change the function of an active MB, the recommended procedure is to put
the module into freeze mode and then change the CODE field of that MB. This is a safe procedure
because the FlexCAN waits for pending CAN bus and MB moving activities to finish before
entering freeze mode. Nevertheless, a mechanism is provided to maintain data coherence when the
CPU writes to the Control and Status word of active MBs out of freeze mode.
Any CPU write access to the C/S word of an MB causes that MB to be excluded from the transmit
or receive processes during the current matching or arbitration round. This mechanism is called
MB deactivation. It is temporary, affecting only for the current match/arbitration round.
The purpose of deactivation is data coherency. The match/arbitration process scans the MBs to
decide which MB to transmit or receive. If the CPU updates the MB in the middle of a match or
arbitration process, the data of that MB may no longer be coherent, therefore that MB is
deactivated.
Even with the coherence mechanism described above, writing to the C/S word of active MBs when
not in freeze mode may produce undesirable results. Examples are:
Freescale Semiconductor
• Matching and arbitration are one-pass processes. If MBs are deactivated after they are
• If a Tx MB containing the lowest ID is deactivated after the FlexCAN has scanned it, then
scanned, no re-evaluation is done to determine a new match/winner. If an Rx MB with a
matching ID is deactivated during the matching process after it was scanned, then this MB
is marked as invalid to receive the frame, and FlexCAN will keep looking for another
matching MB within the ones it has not scanned yet. If it can not find one, then the message
will be lost. Suppose, for example, that two MBs have a matching ID to a received frame,
and the user deactivated the first matching MB after FlexCAN has scanned the second. The
received frame will be lost even if the second matching MB was “free to receive”.
the FlexCAN will look for another winner within the MBs that it has not yet scanned.
Section 21.4.1, “Transmit
MCF5235 Reference Manual, Rev. 2
Process” and
Section 21.4.3, “Receive
Process.” Any form
Functional Overview
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