MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 575

MOD5234 10/100 ETHERNET MODULE

MOD5234-100IR

Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr

Specifications of MOD5234-100IR

Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
its low period. Therefore, synchronized clock I2C_SCL is held low by the device with the longest
low period.
Devices with shorter low periods enter a high wait state during this time (see
all devices concerned have counted off their low period, the synchronized clock I2C_SCL line is
released and pulled high. There is then no difference between the device clocks and the state of the
I2C_SCL line and all the devices start counting their high periods. The first device to complete its
high period pulls the I2C_SCL line low again.
The relative priority of the contending masters is determined by a data arbitration procedure. A
bus master loses arbitration if it transmits logic "1" while another master transmits logic "0". The
losing masters immediately switch over to slave receive mode and stop driving I2C_SDA output
(see
condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration.
Freescale Semiconductor
Figure
I2C_
I2C_
I2C_
I2C_SDA by
Master1
I2C_SDA by
Master2
27-7). In this case the transition from master to slave mode does not generate a STOP
SCL1
SCL2
I2C_SDA
I2C_SCL
SCL
Figure 27-8. Clock Synchronization
Figure 27-7. Arbitration Procedure
Internal Counter Reset
MCF5235 Reference Manual, Rev. 2
Wait
Master 2 Loses Arbitration,
and becomes slave-receiver
Start counting high period
Figure
I
2
C System Configuration
27-8). When
27-7

Related parts for MOD5234-100IR