MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 442

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Enhanced Time Processing Unit (eTPU)
20.6.2.3.2 eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR)
Data transfer request status from all channels are grouped in ETPU_CDTRSR. The bits are
mirrored by the channels’ status/control registers. For more information on data transfers and
channel control registers, see the eTPU User’s Manual and
Status Control Register
20.6.2.3.3 eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)
When a channel interrupt is issued, its status bit is set. If the interrupt status bit remains set and the
microcode issues another channel interrupt, the channel interrupt overflow status (CIOS) bit is set
for that channel. Interrupt overflow status from all channels are grouped in ETPU_CIOSR. The
bits are mirrored by the channels’ status/control registers. For information about channel status
registers and overflow, refer to
(ETPU_CnSCR),” and the eTPU User’s Manual.
20-28
All eTPU channels are logically OR’d to form a single DMA request to the DMA controller.
Figure 20-11. eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR)
Address
31–0
Bits
Reset
Reset
W
W
R
R
The host must write 1 to clear an interrupt overflow status bit.
31
15
0
0
DTRCn
DTRSn
Name
Read:
Write:
30
14
0
0
Table 20-11. ETPU_CDTRSR Field Descriptions
(ETPU_CnSCR).”
29
13
0
0
Channel n data transfer request status.
0 Indicates that channel n has no pending data transfer request.
1 Indicates that channel n has a pending data transfer request.
Channel n data transfer request clear.
0 Keep status bit unaltered
1 Clear status bit.
For details about interrupts refer to the eTPU User’s Manual.
28
12
0
0
Section 20.6.2.4.3, “eTPU Channel n Status Control Register
MCF5235 Reference Manual, Rev. 2
27
11
0
0
26
10
0
0
IPSBAR + 0x1D_0210
25
0
0
9
NOTE
NOTE
24
0
8
0
DTRS
DTRC
DTRS
DTRC
Description
23
0
0
7
22
Section 20.6.2.4.3, “eTPU Channel n
0
0
6
21
0
0
5
20
0
0
4
19
0
0
3
Freescale Semiconductor
18
0
0
2
17
0
0
1
16
0
0
0