MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 540
![MOD5234 10/100 ETHERNET MODULE](/photos/28/91/289101/mod-100ir_sml.jpg)
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
- Current page: 540 of 754
- Download datasheet (13Mb)
UART Modules
26.3.3
The USRn registers, shown in
FIFO.
26-8
Bits
3–0
4
UART Status Registers (USRn)
TxCTS
Name
SB
Address
Reset
Table 26-4. UMR2n Field Descriptions (Continued)
W
Transmitter clear-to-send. If both TxCTS and TxRTS are enabled, TxCTS controls the operation
of the transmitter.
0 UnCTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of UnCTS each time it is
Stop-bit length control. Selects the length of the stop bit appended to the transmitted character.
Stop-bit lengths of 9/16 to 2 bits are programmable for 6–8 bit characters. Lengths of 1-1/16 to
2 bits are programmable for 5-bit characters. In all cases, the receiver checks only for a high
condition at the center of the first stop-bit position, that is, one bit time after the last data bit or
after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, clearing
bit 3 selects one stop bit and setting bit 3 selects two stop bits for transmission.
R
ready to send a character. If UnCTS is asserted, the character is sent; if it is deasseted, the
channel UnTXD remains in the high state and transmission is delayed until UnCTS is
asserted. Changes in UnCTS as a character is being sent do not affect its transmission.
Figure 26-5. UART Status Register (USRn)
RB
0
7
Figure
IPSBAR + 0x0204 (USR0); IPSBAR + 0x0244 (USR1);
FE
MCF5235 Reference Manual, Rev. 2
0
6
0000
0001
0010
0011
0100
0101
0110
26-5, show the status of the transmitter, the receiver, and the
0111
SB
PE
0
5
IPSBAR + 0x0284 (USR2)
5 Bits
1.063
1.125
1.188
1.250
1.313
1.375
1.438
1.500
OE
0
4
6–8 Bits
TXEMP TXRDY FFULL RXRDY
0.563
0.625
0.688
0.750
0.813
0.875
0.938
1.000
Description
0
3
2
0
1000
1001
1010
1011
1100
1101
1110
1111
SB
0
1
5–8 Bits
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
0
0
Freescale Semiconductor
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