MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 16

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

17.7
18.1
18.1.1
18.1.2
18.1.2.1
18.1.3
18.2
18.3
18.3.1
18.3.2
18.3.3
18.3.4
18.3.4.1
18.3.4.2
18.3.4.3
18.3.4.4
18.3.4.5
18.3.5
18.3.5.1
18.4
18.4.1
18.4.2
18.4.3
18.4.4
18.4.5
18.4.6
19.1
19.1.1
19.1.2
19.1.3
19.1.4
19.1.4.1
xvi
Paragraph
Number
Misaligned Operands .................................................................................................. 17-16
Introduction ................................................................................................................... 18-1
External Signal Description .......................................................................................... 18-4
Memory Map/Register Definition ................................................................................ 18-5
SDRAM Example ....................................................................................................... 18-21
Introduction ................................................................................................................... 19-1
Block Diagram .......................................................................................................... 18-1
Overview ................................................................................................................... 18-3
Operation .................................................................................................................. 18-3
DRAM Control Register (DCR) ............................................................................... 18-5
DRAM Address and Control Registers (DACR0/DACR1) ..................................... 18-7
DRAM Controller Mask Registers (DMR0/DMR1) ................................................ 18-9
General Synchronous Operation Guidelines ........................................................... 18-10
Initialization Sequence ............................................................................................ 18-19
SDRAM Interface Configuration ............................................................................ 18-21
DCR Initialization ................................................................................................... 18-22
DACR Initialization ................................................................................................ 18-22
DMR Initialization .................................................................................................. 18-24
Mode Register Initialization ................................................................................... 18-25
Initialization Code ................................................................................................... 18-26
Overview ................................................................................................................... 19-1
Block Diagram .......................................................................................................... 19-1
Features ..................................................................................................................... 19-3
Modes of Operation .................................................................................................. 19-4
Definitions ............................................................................................................ 18-3
Address Multiplexing ......................................................................................... 18-10
Interfacing Example ............................................................................................ 18-15
Burst Page Mode ................................................................................................. 18-15
Auto-Refresh Operation ...................................................................................... 18-17
Self-Refresh Operation ....................................................................................... 18-18
Mode Register Settings ....................................................................................... 18-20
Full and Half Duplex Operation ........................................................................... 19-4
Fast Ethernet Controllers (FEC0 & FEC1)
Synchronous DRAM Controller Module
MCF5235 Reference Manual, Rev. 2
Contents
Chapter 18
Chapter 19
Title
Freescale Semiconductor
Number
Page