MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 742

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Collision handling 19-47
Core
D
Debug
Index-2
signals
system clock 7-15
block diagram 3-1
low-power modes 8-6
pipelines 3-1
registers
BDM
low-power modes 8-11
memory map 32-6
real-time support 32-41
registers
synthesizer status (SYNSR) 7-11
CLKMOD1–0 7-7
CLKOUT 7-7
EXTAL 7-7
RSTOUT 7-7
XTAL 7-7
address (An) 3-3
condition code (CCR) 3-4
data (Dn) 3-2
program counter (PC) 3-3
stack pointer (A7) 3-3
status register (SR) 3-6
vector base (VBR) 3-7
commands
CPU halt 32-19
receive packet 32-21
recommended pinout 32-50
serial interface 32-20
transmit packet 32-22
address attribute trigger (AATR) 32-8
address breakpoint (ABLR, ABHR) 32-9
configuration/status (CSR) 32-10
DUMP 32-30
FILL 32-32
format 32-23
GO 32-33
NOP 32-34
RAREG/RDREG 32-26
RCREG 32-34
RDMREG 32-38
READ 32-27
summary 32-22
WAREG/WDREG 32-27
WCREG 32-37
WDMREG 32-40
WRITE 32-29
–
,
32-44
3-7
MCF5235 Reference Manual, Rev. 2
DMA
DMA controller
E
EMAC
EPORT
signals
taken branch 32-5
trace 32-3
data transfer
channel prioritization 14-14
data transfer 14-3
low-power modes 8-7
programming 14-14
registers
data representation 4-14
instructions
MAC, comparison 4-1
memory map 4-6
opcodes 4-14
operation
registers
low-power modes 8-10
memory map 15-2
registers
data breakpoint/mask (DBR, DBMR) 32-15
program counter breakpoint/mask (PBR,
trigger definition (TDR) 32-17
breakpoint (BKPT) 32-3
debug data (DDATA3–0) 32-3
development serial clock (DSCLK) 32-3
development serial input (DSI) 32-3
development serial output (DSO) 32-3
processor status (PST3–0) 32-3
requests 14-15
auto alignment 14-18
bandwidth control 14-19
requests 14-13
termination 14-19
byte count (BCRn) 14-7
control (DCRn) 14-9
destination address (DARn) 14-7
request control (DMAREQC) 14-5
source address (SARn) 14-6
status (DSRn) 14-8
execution timing 3-25
summary 4-12
fractional 4-9
general 4-3
mask (MASK) 4-11
status (MACSR) 4-6
PBMR) 32-16
,
,
15-1
4-13
Freescale Semiconductor