MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 208

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Reset Controller Module
10.4.2.1 Synchronous Reset Requests
In this discussion, the reference in parentheses refer to the state numbers in
Figure
10-4. All cycle
counts given are approximate.
If the external RESET signal is asserted by an external device for at least four rising CLKOUT
edges (3), if the watchdog timer times out, or if software requests a reset, the reset control logic
latches the reset request internally and enables the bus monitor (5). When the current bus cycle is
completed (6), RSTOUT is asserted (7). The reset control logic waits until the RESET signal is
negated (8) and for the PLL to attain lock (9, 9A) before waiting 512 CLKOUT cycles (1). The
reset control logic may latch the configuration according to the RCON signal level (11, 11A)
before negating RSTOUT (12).
If the external RESET signal is asserted by an external device for at least four rising CLKOUT
edges during the 512 count (10) or during the wait for PLL lock (9A), the reset flow switches to
(8) and waits for the RESET signal to be negated before continuing.
10.4.2.2 Internal Reset Request
If reset is asserted by an asynchronous internal reset source, such as loss of clock (1) or loss of lock
(2), the reset control logic asserts RSTOUT (4). The reset control logic waits for the PLL to attain
lock (9, 9A) before waiting 512 CLKOUT cycles (1). Then the reset control logic may latch the
configuration according to the RCON pin level (11, 11A) before negating RSTOUT (12).
If loss of lock occurs during the 512 count (10), the reset flow switches to (9A) and waits for the
PLL to lock before continuing.
10.4.2.3 Power-On Reset
When the reset sequence is initiated by power-on reset (0), the same reset sequence is followed as
for the other asynchronous reset sources.
10.4.3 Concurrent Resets
This section describes the concurrent resets. As in the previous discussion references in
parentheses refer to the state numbers in
Figure
10-4.
10.4.3.1 Reset Flow
If a power-on reset is detected during any reset sequence, the reset sequence starts immediately (0).
If the external RESET pin is asserted for at least four rising CLKOUT edges while waiting for PLL
lock or the 512 cycles, the external reset is recognized. Reset processing switches to wait for the
external RESET pin to negate (8).
MCF5235 Reference Manual, Rev. 2
10-8
Freescale Semiconductor