MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 275

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

13.2.1.4 Interrupt Request Level Register (IRLRn)
This 7-bit register is updated each machine cycle and represents the current interrupt requests for
each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. This register output
from both interrupt controllers (INTC0 & INTC1) are combined encoded into the 3-bit priority
interrupt level driven to the processor core.
13.2.1.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn)
Each time an IACK is performed, the interrupt controller responds with the vector number of the
highest priority source within the level being acknowledged. In addition to providing the vector
number directly for the byte-sized IACK read, this 8-bit register is also loaded with information
about the interrupt level and priority being acknowledged. This register provides the association
between the acknowledged “physical” interrupt request number and the programmed interrupt
level/priority. The contents of this read-only register are described in
Freescale Semiconductor
Bits
7–1
0
Name
Figure 13-8. IACK Level and Priority Register (IACKLPRn)
IRQ
Address
Address
—
Reset
Figure 13-7. Interrupt Request Level Register (IRLRn)
Reset
W
W
R
R
Interrupt requests. Represents the prioritized active interrupts for each level.
0 There are no active interrupts at this level
1 There is an active interrupt at this level
Reserved
Table 13-10. IRQLRn Field Descriptions
0
0
0
7
7
IPSBAR + 0x00_0C18 (INTC0); IPSBAR + 0x00_0D18 (INTC1)
IPSBAR + 0x00_0C19 (INTC0); IPSBAR + 0x00_0D19 (INTC1)
MCF5235 Reference Manual, Rev. 2
0
0
6
6
LEVEL
0
0
5
5
IRQ
0
0
4
4
Description
0
0
3
3
2
0
2
0
PRI
Figure 13-8
0
0
1
1
Memory Map/Register Definition
0
0
0
0
0
and
Table
13-11.
13-11