MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 584

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

I
ENMASR
NXMAR
27.6.5 Generation of Repeated START
After the data transfer, if the master still wants the bus, it can signal another START followed by
another slave address without signalling a STOP, as in the following example.
RESTART MOVE.B I2CR,-(A7)
27.6.6 Slave Mode
In the slave interrupt service routine, software should poll the I2SR[IAAS] bit to determine if the
controller has received its slave address. If IAAS is set, software should set the transmit/receive
mode select bit (I2CR[MTX]) according to the I2SR[SRW]. Writing to the I2CR clears the IAAS
automatically. The only time IAAS is read as set is from the interrupt at the end of the address cycle
where an address match occurred; interrupts resulting from subsequent data transfers will have
IAAS cleared. A data transfer can now be initiated by writing information to I2DR for slave
transmits, or read from I2DR in slave-receive mode. A dummy read of I2DR in slave/receive mode
releases I2C_SCL, allowing the master to send data.
In the slave transmitter routine, I2SR[RXAK] must be tested before sending the next byte of data.
Setting RXAK means an end-of-data signal from the master receiver, after which software must
switch it from transmitter to receiver mode. Reading I2DR then releases I2C_SCL so that the
master can generate a STOP signal.
27.6.7 Arbitration Lost
If several devices try to engage the bus at the same time, one becomes master. Hardware
immediately switches devices that lose arbitration to slave receive mode. Data output to I2C_SDA
stops, but I2C_SCL is still generated until the end of the byte during which arbitration is lost. An
interrupt occurs at the falling edge of the ninth clock of this transfer with I2SR[IAL] = 1 and
I2CR[MSTA] = 0.
27-16
2
C Interface
EXTB.L D1
SUBI.L #1,D1;
BNE.S NXMAR
LAMAR BSET.B #3,I2CR
BRA NXMAR
BCLR.B #5,I2CR
MOVE.B I2DR,RXBUF
BSET.B #2, (A7)
MOVE.B (A7)+, I2CR
MOVE.B CALLING,-(A7)
MOVE.B CALLING,-(A7)
MOVE.B (A7)+, I2DR
MCF5235 Reference Manual, Rev. 2
;Not last one or second last
;Disable ACK
;Last one, generate STOP signal
;Read data and store RTE
;Repeat START (RESTART)
;Transmit the calling address, D0=R/W-
Freescale Semiconductor