MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 432
![MOD5234 10/100 ETHERNET MODULE](/photos/28/91/289101/mod-100ir_sml.jpg)
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
- Current page: 432 of 754
- Download datasheet (13Mb)
Enhanced Time Processing Unit (eTPU)
20.6.2.1.2 eTPU Coherent Dual-Parameter Controller Register (ETPU_CDCR)
ETPU_CDCR configures and controls dual-parameter coherent transfers. For more information,
refer to the eTPU User’s Manual.
20-18
Address
Figure 20-4. eTPU Coherent Dual-Parameter Controller Register (ETPU_CDCR)
Bits
5–1
Reset
Reset
6
0
W
W
R
R PWIDTH
STS
31
15
0
0
Name
GTBE
Table 20-3. ETPU_MCR Bit Field Descriptions (Continued)
VIS
—
30
14
0
0
SCM visibility. Determines SCM visibility to the internal bus interface and resets the MISC
state (but SCMMISEN keeps its value).
0 SCM is not visible to the internal bus. Accessing SCM address space issues a bus error.
1 SCM is visible to the internal bus. The MISC state is reset.
This bit is write protected when any of the engines are not in halt or stop states. When
VIS=1, the ETPU_ECR[MDIS] bit is write protected, and only 32-bit aligned SCM writes are
supported. The value written to SCM is unpredictable if other transfer sizes are used.
Reserved.
Global time base enable. Enables time bases in both engines, allowing them to be started
synchronously. This enables the eTPU time base to all start synchronously.
1 time base in the eTPU engine are enabled to run.
0 time base in the engine are disabled to run.
29
13
0
0
CTBASE
28
12
0
0
MCF5235 Reference Manual, Rev. 2
PARM0
27
11
0
0
26
10
0
0
IPSBAR + 0x1D_0004
25
0
0
9
24
0
0
8
Description
WR
23
0
0
7
22
0
6
0
PBBASE
21
0
0
5
20
0
0
4
PARM1
19
0
0
3
Freescale Semiconductor
18
0
0
2
17
0
0
1
16
0
1
0
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