MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 302

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

DMA Controller Module
14.4.4.2 Auto-Alignment
Auto-alignment allows block transfers to occur at the optimal size based on the address, byte
count, and programmed size. To use this feature, DCRn[AA] must be set. The source is
auto-aligned if DCRn[SSIZE] indicates a transfer size larger than DCRn[DSIZE]. Source
alignment takes precedence over the destination when the source and destination sizes are equal.
Otherwise, the destination is auto-aligned. The address register chosen for alignment increments
regardless of the increment value. Configuration error checking is performed on registers not
chosen for alignment.
If BCRn is greater than 16, the address determines transfer size. Bytes, words, or longwords are
transferred until the address is aligned to the programmed size boundary, at which time accesses
begin using the programmed size.
If BCRn is less than 16 at the start of a transfer, the number of bytes remaining dictates transfer
size. For example, AA = 1, SARn = 0x0001, BCRn = 0x00F0, SSIZE = 00 (longword), and DSIZE
= 01 (byte). Because SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on
destination registers. The access sequence is as follows:
14-18
1. Read byte from 0x0001—write 1 byte, increment SARn.
2. Read word from 0x0002—write 2 bytes, increment SARn.
3. Read longword from 0x0004—write 4 bytes, increment SARn.
4. Repeat longwords until SARn = 0x00F0.
5. Read byte from 0x00F0—write byte, increment SARn.
A[31:0], SIZ[1:0]
OE, BE/BWE
CSx, AS
DREQ
D[31:0]
CLKIN
R/W
TIP
TA
TS
n
0
Figure 14-11. Single-Address DMA Transfer
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